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Failure-Tolerant Self-Testing Driver/Receiver

IP.com Disclosure Number: IPCOM000039859D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 67K

Publishing Venue

IBM

Related People

Balliet, L: AUTHOR [+2]

Abstract

This article describes a circuit arrangement that isolates line faults from circuit faults and permits self-test even in the presence of an incoming signal. The increased sophistication of electronic equipment makes automated fault-isolation extremely important for many systems. One such application is found in the automotive industry where technicians are not highly skilled in electronic circuit maintenance. Computerized testing in this case must isolate faults to a single unit or component. The interface between assemblies is of special concern. Each electronics assembly should be self-testing and be able to differentiate between faults caused by its own driver/receiver, the interconnecting cable and/or the interfacing unit. Fig.

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Failure-Tolerant Self-Testing Driver/Receiver

This article describes a circuit arrangement that isolates line faults from circuit faults and permits self-test even in the presence of an incoming signal. The increased sophistication of electronic equipment makes automated fault-isolation extremely important for many systems. One such application is found in the automotive industry where technicians are not highly skilled in electronic circuit maintenance. Computerized testing in this case must isolate faults to a single unit or component. The interface between assemblies is of special concern. Each electronics assembly should be self-testing and be able to differentiate between faults caused by its own driver/receiver, the interconnecting cable and/or the interfacing unit. Fig. 1 shows a conventional, non- redundant, driver/receiver design that attempts to solve this problem. During normal operation, switches 1 and 2 are closed and switch 3 is open. The driver D and receiver R are connected to a similar circuit. When a test mode is initiated, switches 1 and 2 are opened and switch 3 is closed. Test patterns are wrapped from the interface logic through switch 3 and back through the receiver. However, the tests become invalid if faults occur in the switches or circuit connections. External switches must be eliminated totally. The circuit arrangement disclosed herein solves this problem and additionally tests the continuity of the internal and external connections.

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Fig. 2 is a functional diagram of the circuit of this disclosure. No conventional switches are used. The circuit consists of a special dual-mode driver 4, a dual- mode receiver 5, and a test voltage-controlled current source (VCCS) 6. Consider the circuit to be an integrated circuit with several connections 8 between the chip and external connector. The driver output and receiver inputs are wired through the connections. The key to the circuit operation is the dual- mode driver/ receiver. They operate in a voltage mode under normal operation, and in the current mode when in a test mode. A test logic level command, which also inputs into the test VCCS, selects the mode. The driver design is such that it acts like a voltage driver or a voltage-mode receiver while the "transmit enable" input is inactive during normal operation, and a current-mode receiver in test mode. The test data generated by the test VCCS 6 actually enters through the output of the driver and is sensed at the input. The purpose is to test the output devices of the driver which are in all probability the devices which will fail, due to current surges, or electrostatic discharge. In test mode, the driver hangs on the line (without driving the line) following any voltage and measuring any current.

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When in the test mode, the test VCCS accepts the test pattern from the CPU and transforms it to a current input onto the bus. The test pattern generated by the CPU is routed out throu...