Browse Prior Art Database

Surface Solder Package

IP.com Disclosure Number: IPCOM000039868D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Engle, SR: AUTHOR [+3]

Abstract

A packaging concept for the application of chip and substrate technologies to a surface solder packaging scheme is described in this article. A substrate 1 (Fig. 1), having metallized ceramic/metallized ceramic polyimide circuitry 2 on the top side, has edge clips 3 attached to provide an electrical connection between the circuitry 2 and a soldered surface (not seen). A chip 4 is attached using standard controlled collapse chip connector technology. The electrical connection between the clip leads 5 and the substrate circuitry 2 is established by reflowing solder on the clips 3 during chip joining. (Image Omitted) A cap 5 (Fig. 2) of some suitable material, is attached to substrate 1 by epoxy 6. Thermal grease 7, for removal of heat from the chip 4, can be used, if needed.

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Surface Solder Package

A packaging concept for the application of chip and substrate technologies to a surface solder packaging scheme is described in this article. A substrate 1 (Fig.
1), having metallized ceramic/metallized ceramic polyimide circuitry 2 on the top side, has edge clips 3 attached to provide an electrical connection between the circuitry 2 and a soldered surface (not seen). A chip 4 is attached using standard controlled collapse chip connector technology. The electrical connection between the clip leads 5 and the substrate circuitry 2 is established by reflowing solder on the clips 3 during chip joining.

(Image Omitted)

A cap 5 (Fig. 2) of some suitable material, is attached to substrate 1 by epoxy 6. Thermal grease 7, for removal of heat from the chip 4, can be used, if needed. A protective coating 8 is used to cover those portions of circuitry outside of the cap
5.

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