Browse Prior Art Database

Two-Buffer System With Sequential Full Image Transfer

IP.com Disclosure Number: IPCOM000039878D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Evangelisti, CJ: AUTHOR [+2]

Abstract

A two-buffer system for providing images on a raster display without resulting artifacts is disclosed and comprises first and second frame buffers having dual-port random-access memories (RAMs) with each buffer alternately refreshing the display and being updated by the other frame buffer via feedback, and logic circuitry for controlling the refreshing and updating cycles of the first and second frame buffers. The provided system allows fast sequential transfer of the full image from one buffer to the other without the intervention of a microprocessor, as is required in the systems known in the art. Turning to the figure, the two-buffer system 10 for providing images on a display is seen to comprise frame buffers 15 and 20, flip- flops 25 and 30, exclusive OR gate (XOR) 35, AND gates 42, 44, 46 and 48, and OR gate 50.

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Two-Buffer System With Sequential Full Image Transfer

A two-buffer system for providing images on a raster display without resulting artifacts is disclosed and comprises first and second frame buffers having dual- port random-access memories (RAMs) with each buffer alternately refreshing the display and being updated by the other frame buffer via feedback, and logic circuitry for controlling the refreshing and updating cycles of the first and second frame buffers. The provided system allows fast sequential transfer of the full image from one buffer to the other without the intervention of a microprocessor, as is required in the systems known in the art. Turning to the figure, the two- buffer system 10 for providing images on a display is seen to comprise frame buffers 15 and 20, flip- flops 25 and 30, exclusive OR gate (XOR) 35, AND gates 42, 44, 46 and 48, and OR gate 50. The inputs into the logic circuitry include a switch buffer signal 53 (SWBUFF) and a frame period signal 57 (FP). In starting, with the SWBUFF and FP signals 53 and 57 at zero, both flip- flops 25 and 30 have a zero output, and thus the XOR gate has a zero output. As a result, the output of AND gate 42 is one and information from frame buffer 15 may flow therethrough, while AND gates 44, 46, and 48 have a zero output and are closed to the flow of information. With AND gate 42 being high, the output of OR gate 50 is high, and information is sent from frame buffer 15 through AND gate 42 and OR gate 50 to refresh the display. On the rising side of the first frame pulse signal 57 after the switch buffer signal 53 goes high, the Q output of flip-flop 25 goes high, forcing the output of XOR gate 35 high. As a result, AND gates 42 and 44 close to information (output zero), while AND gates 46 and 48 open (output one). Thus, frame buffer 20 now refreshes the display with information via AN...