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On-Chip Decoupling Capacitor for Logic VLSI Chips

IP.com Disclosure Number: IPCOM000039886D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+2]

Abstract

Power supply noise reduction is achieved by distributed on-chip decoupling capacitors provided and integrated in logic VLSI chips, the logic cells of which are realized in CMOS technology. Unused cells are modified to form the capacitors connected to power supply line VH and to ground GD. Power supply noise is mainly due to current changes WI/Wt in the inductances of the module and chip wiring. These current changes are caused by the switching of the logic circuits and the embedded arrays. As normally only 60% of the cells of logic chips are used, unused cells are employed as distributed decoupling capacitors between power supply line VH and ground GD, thus reducing the power supply noise. A trade- off between noise and the number of switching circuits is possible.

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On-Chip Decoupling Capacitor for Logic VLSI Chips

Power supply noise reduction is achieved by distributed on-chip decoupling capacitors provided and integrated in logic VLSI chips, the logic cells of which are realized in CMOS technology. Unused cells are modified to form the capacitors connected to power supply line VH and to ground GD. Power supply noise is mainly due to current changes WI/Wt in the inductances of the module and chip wiring. These current changes are caused by the switching of the logic circuits and the embedded arrays. As normally only 60% of the cells of logic chips are used, unused cells are employed as distributed decoupling capacitors between power supply line VH and ground GD, thus reducing the power supply noise. A trade- off between noise and the number of switching circuits is possible. The decoupling capacitors, filling the unused cells, are formed by CMOS capacitors existing between the channel and gate of an N-channel FET Cn and a P-channel FET Cp. Drain and source of FET Cp are jointly connected to power supply line VH, whereas the gate is connected to ground GD. Drain and source of FET Cn are jointly connected to ground GD, whereas the gate of this FET is connected to power supply line VH.

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