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Selective Node Dielectric Thinning of Semiconductor Dynamic Memory Cells

IP.com Disclosure Number: IPCOM000039895D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 86K

Publishing Venue

IBM

Related People

Kenney, DM: AUTHOR

Abstract

Increased storage node capacitance of semiconductor dynamic memory cells can be realized by a combination of device structural changes, new process features and doping steps leading to cell density improvements. Storage node capacitance is increased by thinning the storage dielectric and through the introduction of an additional boron diffusion in the storage node. (Image Omitted) Fig. 1 of the improved process shows a P substrate with three dielectric films on top, i.e., a thermal oxide, chemical vapor deposition (CVD) nitride and CVD oxide. Fig. 2 shows photoresist placed on top of the dielectric films and patterned to form a storage node (S/N) and a bit line (B/L). Both nodes are implanted with boron and arsenic. Fig. 3 shows another mask placed over the storage node, followed by a second arsenic implant on the bit line.

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Selective Node Dielectric Thinning of Semiconductor Dynamic Memory Cells

Increased storage node capacitance of semiconductor dynamic memory cells can be realized by a combination of device structural changes, new process features and doping steps leading to cell density improvements. Storage node capacitance is increased by thinning the storage dielectric and through the introduction of an additional boron diffusion in the storage node.

(Image Omitted)

Fig. 1 of the improved process shows a P substrate with three dielectric films on top, i.e., a thermal oxide, chemical vapor deposition (CVD) nitride and CVD oxide. Fig. 2 shows photoresist placed on top of the dielectric films and patterned to form a storage node (S/N) and a bit line (B/L). Both nodes are implanted with boron and arsenic. Fig. 3 shows another mask placed over the storage node, followed by a second arsenic implant on the bit line. After the mask is removed, a thermal oxidation step is initiated. Fig. 4 shows the thermal diffusion of the dopants and oxidation of the BL. The higher bit line arsenic concentration effectively reduces the boron diffusion concentration so that little or no boron is diffused before the bit line arsenic is diffused. Also, the BL oxidation serves to getter boron and assists in reducing the diffusion of boron. The net effect is a high concentration of boron in the storage node region in a self-aligned manner without a similar boron enrichment in the bit line region. Such a boron distribution is preferred to keep the bit line capacitance low and the storage node capacitance high. The higher boron concentration allows closer node-to-node and node-to-bit line spacing. Also, the cell device channel length may be reduced due to a high concentration of boron in the channel region. Thus, cell density can be improved by utilizing more of the isolation area between cells. Such a device may have relatively high VT, thus reducing the voltage that can be placed on the node diffusion. The stored charge level at the node can be maintained by using a sufficiently thin node dielectric so as to maintain the electric field. Fig. 5 shows the CVD oxide, shown in Fig. 1, being used as a mask to remove the initial oxi...