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Dynamic Tri-State Latch/Memory Sense Amplifier

IP.com Disclosure Number: IPCOM000039897D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Furman, A: AUTHOR

Abstract

This semiconductor circuit provides a temporary memory storage location for memory bit lines, with an attendant improvement in access and cycle time by permitting early restore before data out is permanently latched in static registers. Most memories utilize dynamic bit lines due to power/performance considerations involved with static sense amplifiers. Memory restore cannot be initiated until data out is permanently latched in a static data storage register. If the data register clock is not coincident with the memory data out, memory restore is delayed, causing a slower cycle time. Through the utilization of a temporary data holding means before memory data out is permanently latched in a static register, an early memory restore is permitted and cycle time is enhanced.

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Dynamic Tri-State Latch/Memory Sense Amplifier

This semiconductor circuit provides a temporary memory storage location for memory bit lines, with an attendant improvement in access and cycle time by permitting early restore before data out is permanently latched in static registers. Most memories utilize dynamic bit lines due to power/performance considerations involved with static sense amplifiers. Memory restore cannot be initiated until data out is permanently latched in a static data storage register. If the data register clock is not coincident with the memory data out, memory restore is delayed, causing a slower cycle time. Through the utilization of a temporary data holding means before memory data out is permanently latched in a static register, an early memory restore is permitted and cycle time is enhanced. Memory data out lines of a static memory are typically dynamically precharged and differentially discharged. Dynamic memories are usually single ended but may be differentially sensed. In this case, the local sense amplifier is dynamically precharged and differentially discharged. Thus, the bit line states are as follows:
1) 1-1 Restore condition.

2) 0-1 A polarity of the data.

3) 1-0 Another polarity of the data.

4) 0-0 Cannot normally occur without a fault. The above bit line or local amplifier states satisfy the requirements of the circuit, shown in the figure, for storing data temporarly on the capacitor-loaded output of an ungated/unclocked tri-state amplifier. Transistors T1 and T2 sample and amplify one of the differential pair of bit lines B0, B1 and the output of this inverter drives T4 as a pull-down for capacitor CL. T3 samples the other bit line of the differential pair and is the charge-up for capacitor CL. 1) 1-1 Restore condition. In the restore state, both bit lines are precharged high, and both P channel devices (T1 and T3) are off. Device T2 is on and grounds the gate of T4. Because both T3 and T4 are off, their output node CL is floating in a high impedance state. When the memory is read or write accessed, one of the bit lines of the differential pair falls to ground. 2) 0-1 A polarity of the data. If the left bit line falls, T3 turns on and charges CL high at a rate dependent on the device size and the level to which the left bit line falls. Because the right bit line remains high, node MID remains at ground and T4 remains off. After CL is charged, the memory may be restored immediately. The left bit line is driven plus by restore devices (not shown), turning T3 off. Because the right bit line never changed state, node MID remains at ha...