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Carry Signal Generation for High-Speed Full Adder

IP.com Disclosure Number: IPCOM000039903D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Helwig, K: AUTHOR

Abstract

An improved circuit for generating the carry signal is described in conjunction with XOR circuit and (CMOS) inverters forming full adder circuits (Figs. 1 and 2) with inputs A, B, Cin and outputs S and Cout for the sum and carry-out function, respectively. The carry circuit consists of two P-FETs T1 and T4 and two N-FETs T2 and T3 which are used as transfer devices. The sources of these four FETs are driven by CMOS inverters I, whereas the gates are controlled by the true and inverted output X, X- of the XOR1 circuit. The structure of the carry circuit may be kept substantially identical for the carry-out true (Fig. 2) and the carry-out complement (Fig. 1) function, the only exception being the crossing of the X and the X- signal lines, as indicated in Fig. 2.

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Carry Signal Generation for High-Speed Full Adder

An improved circuit for generating the carry signal is described in conjunction with XOR circuit and (CMOS) inverters forming full adder circuits (Figs. 1 and 2) with inputs A, B, Cin and outputs S and Cout for the sum and carry-out function, respectively. The carry circuit consists of two P-FETs T1 and T4 and two N-FETs T2 and T3 which are used as transfer devices. The sources of these four FETs are driven by CMOS inverters I, whereas the gates are controlled by the true and inverted output X, X- of the XOR1 circuit. The structure of the carry circuit may be kept substantially identical for the carry-out true (Fig. 2) and the carry-out complement (Fig. 1) function, the only exception being the crossing of the X and the X- signal lines, as indicated in Fig. 2. Devices T1 to T4 and the appropriate signals X and X- prevent a short-circuiting of signals A- and C-in (A and Cin, respectively, in Fig. 2) which are applied to the sources of T1 to T4. The Cout signal delay is equal or better compared with the sum output S. Allowing a simpler layout, the proposed carry circuit thus contributes to an optimized full adder design.

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