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Folded Bitline Configuration

IP.com Disclosure Number: IPCOM000039905D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 119K

Publishing Venue

IBM

Related People

Hwang, W: AUTHOR [+2]

Abstract

Dynamic random-access memory cells can be constructed with greater density by using folded bitlines each connected to alternate cells or by slightly offsetting adjacent cells in rows and columns. Fig. 1 schematically illustrates a memory cell having trench capacitors 1 and 2 in substrate 3 each connected to a respective source 4 and sharing a common drain junction 5 and common bitline 6. Word lines 7 and 8 are connected to respective polysilicon transfer gates. The bitline is constructed using one layer of interconnection line among its associated cells. An arrangement for folded bitlines is shown in Fig. 2. True bitlines BL1-BL4 and complementary bitlines BL1-BL4 interconnect in zigzag fashion with bitline contacts 10 in alternate columns.

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Folded Bitline Configuration

Dynamic random-access memory cells can be constructed with greater density by using folded bitlines each connected to alternate cells or by slightly offsetting adjacent cells in rows and columns. Fig. 1 schematically illustrates a memory cell having trench capacitors 1 and 2 in substrate 3 each connected to a respective source 4 and sharing a common drain junction 5 and common bitline 6. Word lines 7 and 8 are connected to respective polysilicon transfer gates. The bitline is constructed using one layer of interconnection line among its associated cells. An arrangement for folded bitlines is shown in Fig. 2. True bitlines BL1-BL4 and complementary bitlines BL1-BL4 interconnect in zigzag fashion with bitline contacts 10 in alternate columns. Each of a pair of true and complementary bitlines connects on the same output side of its respective sense amplifier SA or SA at opposite ends of the array, and each pair of bitlines also connects with column decoders at either end of the array. This arrangement better accommodates the area requirements of the sense amplifiers and column decoders. An alternative denser cell arrangement is shown in Fig. 3 in which memory cells are shifted slightly in row and column positions to accommodate closer word lines. True bitlines BL1-BL4 and complementary bitlines BL1-BL4 remain in a parallel zigzag configuration but the row position of alternative cells is offset. Work line pairs (WL1 and WL1, WL2 and WL2,...