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Tri-State Driver in Complementary Metal-Oxide Semiconductor Technology

IP.com Disclosure Number: IPCOM000039906D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Hansen, AA: AUTHOR

Abstract

This article describes a tri-state driver in complementary metal-oxide semiconductor (CMOS) technology with full potential data out port using only four transistors and providing improved performance within a small area. The circuit, shown in the drawing, is a tri-state driver. Q1 and Q2 are P-ch field-effect transistors (FETs), and Q3 and Q4 are N-ch FETs. The capacitance C is a normal capacitance realized when fabricating CMOS circuits, and not an added device. The circuit performs as the truth table shown below. The circuit is controlled by the enable signal P1. When the enable signal is 0, the output devices Q2 and Q4 are OFF, leaving the output P3 floating or at a high impedance.

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Tri-State Driver in Complementary Metal-Oxide Semiconductor Technology

This article describes a tri-state driver in complementary metal-oxide semiconductor (CMOS) technology with full potential data out port using only four transistors and providing improved performance within a small area. The circuit, shown in the drawing, is a tri-state driver. Q1 and Q2 are P-ch field-effect transistors (FETs), and Q3 and Q4 are N-ch FETs. The capacitance C is a normal capacitance realized when fabricating CMOS circuits, and not an added device. The circuit performs as the truth table shown below. The circuit is controlled by the enable signal P1. When the enable signal is 0, the output devices Q2 and Q4 are OFF, leaving the output P3 floating or at a high impedance. When the enable signal is at logical 1, both Q2 and Q4 are ON and the output P3 can be charged or discharged through Q2 or Q4, respectively, depending on the polarity of data at port P2. The full potential is realized at the output.

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