Browse Prior Art Database

Technique for Assigning Responsibilities to Separate Microprocessors in a Multi-Processor System

IP.com Disclosure Number: IPCOM000039919D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+5]

Abstract

A technique is described whereby multi-processor systems sharing the same memory are able to execute the same microcode. The concept eliminates the need for separate microcode, to be included at each microprocessor, by using a method of assigning separate tasks to each of the microprocessors. By enabling several microprocessors, which have separate operational functions, to execute identical microcode, similar functions, such as performing power-on diagnostics and initialization of common microcode, will reduce the overall memory required in the system. A timing control logic unit 10, as shown in the figure, is provided to interleave microprocessor access to the memory unit of the system. Interrupt line 11 at microprocessor #1 is set to logical state of "1".

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 86% of the total text.

Page 1 of 2

Technique for Assigning Responsibilities to Separate Microprocessors in a Multi-Processor System

A technique is described whereby multi-processor systems sharing the same memory are able to execute the same microcode. The concept eliminates the need for separate microcode, to be included at each microprocessor, by using a method of assigning separate tasks to each of the microprocessors. By enabling several microprocessors, which have separate operational functions, to execute identical microcode, similar functions, such as performing power-on diagnostics and initialization of common microcode, will reduce the overall memory required in the system. A timing control logic unit 10, as shown in the figure, is provided to interleave microprocessor access to the memory unit of the system. Interrupt line 11 at microprocessor #1 is set to logical state of "1". Interrupt line 12 on microprocessor #2 is set to a logical state of "0". If additional microprocessors are in the system, then they are also set to logical state "0". On power-up, the interrupts are disabled and all the microprocessors execute the same power-on diagnostics and initialization microcode. At completion of the diagnostics and initialization, the interrupts will be enabled. Microprocessor #1 will then branch to a different area of microcode in order to perform its designated function. The other microprocessors will not be interrupted and therefore will continue their program flow, allowing performance...