Browse Prior Art Database

Complementary Output Clock Driver

IP.com Disclosure Number: IPCOM000039920D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Gorga, KJ: AUTHOR

Abstract

When using high speed vendor logic families such as Fast, Schottky and Advanced Schottky, a true and complement clock is often required. This is because some devices, such as shift registers, clock on the falling clock edge and other devices, such as counters, clock on the rising clock edge. In designs that require these high speed logic families, the 6 nanoseconds of inverter gate delay skew the clock off too far to meet other system timings. Emitter coupled logic, with its low scale integration and non-transistor-to-transistor logic (TTL) compatible signal and supply voltage levels, is not a viable alternative. Using a 2X oscillator and a flip-flop is not practical when a system clock of 60 MHz is required.

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Complementary Output Clock Driver

When using high speed vendor logic families such as Fast, Schottky and Advanced Schottky, a true and complement clock is often required. This is because some devices, such as shift registers, clock on the falling clock edge and other devices, such as counters, clock on the rising clock edge. In designs that require these high speed logic families, the 6 nanoseconds of inverter gate delay skew the clock off too far to meet other system timings. Emitter coupled logic, with its low scale integration and non-transistor-to- transistor logic (TTL) compatible signal and supply voltage levels, is not a viable alternative. Using a 2X oscillator and a flip-flop is not practical when a system clock of 60 MHz is required. This is the upper limit of TTL oscillators, and a 120 MHz oscillator could not be obtained. The above circuit will deliver a true and complement clock with less than 1.5 nanoseconds of worst-case skew. The oscillator is run into an exclusive OR gate with one gate's input tied high and the other low. The gate tied low will produce a true clock, and the gate tied high will produce the complement. If both devices are in the same package, their relative delays will be equal and the worst-case skew between the high and low input gate will be only 1.5 nanoseconds.

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