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Low Resolution Tach Uses Dual Edge Technique to Boost Performance

IP.com Disclosure Number: IPCOM000039949D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Champion, JR: AUTHOR [+2]

Abstract

A microprocessor-based dual-edge technique of analyzing a low resolution tach signal nearly doubles the effective resolution of the tach. The technique also utilizes a software phase locked loop to generate a higher frequency tach signal. This allows the performance of a higher cost tach technology to be achieved with a low cost technology. The duty cycle of a tach signal will change with the age of the sensor, tach wheel wobble, contamination, and original parts toler- Continued ances. This usually forces the use of the information contained in only one edge of the signal (leading-edge or trailing-edge). The following technique of processing both edges of the tach signal is insensitive to the above variations and allows a higher frequency tach signal to be generated with better resolution than a single-edge technique.

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Low Resolution Tach Uses Dual Edge Technique to Boost Performance

A microprocessor-based dual-edge technique of analyzing a low resolution tach signal nearly doubles the effective resolution of the tach. The technique also utilizes a software phase locked loop to generate a higher frequency tach signal. This allows the performance of a higher cost tach technology to be achieved with a low cost technology. The duty cycle of a tach signal will change with the age of the sensor, tach wheel wobble, contamination, and original parts toler- Continued ances. This usually forces the use of the information contained in only one edge of the signal (leading-edge or trailing-edge). The following technique of processing both edges of the tach signal is insensitive to the above variations and allows a higher frequency tach signal to be generated with better resolution than a single-edge technique. A microprocessor is interrupted on both leading and trailing edges of a tach signal (see figure). The processor measures the time between each interrupt. At each interrupt the most recent period is calculated using the accumulated time of trailing-edge to trailing-edge or leading-edge to leading-edge. The tach period information is then used to update a clock that interrupts the processor at a rate which is an integral multiple of the tach frequency (the clock interrupt frequency used in this discussion is five times the tach frequency). The clock periods are an exact replica of the tach periods but delayed about 3/4 of one tach period. The clock intervals are calculated based upon half-periods. During odd-numbered clock half-periods, the clock is run using a time interval that is one fi...