Browse Prior Art Database

Intercarrier Connected Module

IP.com Disclosure Number: IPCOM000039957D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Covino, JJ: AUTHOR [+2]

Abstract

This technique provides for the interconnection of plastic single-chip carriers, or dual in-line packages (DIPs), into a module that can be inserted into a 100-mil card. Pins on 100-mil grid are inserted into a card, and the remaining pins are interconnected to provide a module unit. The technique allows a chip with 25% greater input/output (I/O) to be packaged in the same card area. It also provides single-chip carrier test capability, module rework and stackability. (Image Omitted) Two methods of achieving this package are described. The first method is shown in Figs. 1 and 2. Here, the lead frame for DIP B is bent in the opposite direction from DIP A. DIP B is then flipped. This allows same pad interconnection between chips. The second method is shown in Figs. 3 and 4. Both chips/DIPs are face up.

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Intercarrier Connected Module

This technique provides for the interconnection of plastic single-chip carriers, or dual in-line packages (DIPs), into a module that can be inserted into a 100-mil card. Pins on 100-mil grid are inserted into a card, and the remaining pins are interconnected to provide a module unit. The technique allows a chip with 25% greater input/output (I/O) to be packaged in the same card area. It also provides single-chip carrier test capability, module rework and stackability.

(Image Omitted)

Two methods of achieving this package are described. The first method is shown in Figs. 1 and 2. Here, the lead frame for DIP B is bent in the opposite direction from DIP A. DIP B is then flipped. This allows same pad interconnection between chips. The second method is shown in Figs. 3 and 4. Both chips/DIPs are face up. Pads (A0, A11), (A1, A10), (A2, A8), and (A4, A7) must have similar functions, e.g., SARs.

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