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Shift Register Latch Circuit With Predictable Transfer Characteristics and Differential Cascode Voltage Switch Logic Compatibility

IP.com Disclosure Number: IPCOM000039970D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Thoma, NG: AUTHOR

Abstract

A technique is described whereby a conventional shift register latch (SRL) circuit, which typically uses data inverters to obtain a two- phase data signal for a data write operation, is modified so as to obtain predictable transfer characteristics and compatibility with differential cascode voltage switch (DCVS) logic circuitry. In prior art, inverter circuitry was used to invert the state of the data input so that the state of cross-coupled memory circuits may be changed. However, symmetric write characteristics were difficult to obtain due to the transfer characteristics of the two data paths, where one path was fed directly to the gate of a transistor while the other path went to the data inverter of the gate.

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Shift Register Latch Circuit With Predictable Transfer Characteristics and Differential Cascode Voltage Switch Logic Compatibility

A technique is described whereby a conventional shift register latch (SRL) circuit, which typically uses data inverters to obtain a two- phase data signal for a data write operation, is modified so as to obtain predictable transfer characteristics and compatibility with differential cascode voltage switch (DCVS) logic circuitry. In prior art, inverter circuitry was used to invert the state of the data input so that the state of cross-coupled memory circuits may be changed. However, symmetric write characteristics were difficult to obtain due to the transfer characteristics of the two data paths, where one path was fed directly to the gate of a transistor while the other path went to the data inverter of the gate. If an equal voltage transfer should occur, then the timing would not match, resulting in unequal setup times for positive and negative input signals. An example of such a circuit can be seen in [*]. The improved SRL circuit, as shown in the figure, is a modified latch L1/L2 circuit pair with transfer gate inputs to L1. There are a varying number of inputs, with every circuit having a specific input for the level sensitive scan design (LSSD) in data and either one or two data inputs. Latch L1 consists of transistors T2 through T6 and is configured such that during the C clock time, which is latch L1 write time, a none logic signal is used to interrupt the feedback in the L1 stage by shutting off T6, a low threshold voltage NMOS transistor. The none logic signal is the complement of either the C clock or the A clock. This reconfigures the L1 circuit into two cascaded inverters, the first consisting of T2 and T3, which drive the second consisting of T4 and T5 so as to provide a high input impedance to latch L2, a conventional cross-coupled storage circuit. The interrupted feedback circuit in the L1 stage eliminates the nee...