Browse Prior Art Database

# Tolerance-Compensated Circuit for Cmos Vlsi Clock Distribution

IP.com Disclosure Number: IPCOM000039972D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 45K

IBM

## Related People

Mather, AN: AUTHOR

## Abstract

In a conventional computer system, clock distribution on chip clocks is distributed through a tree of AND-OR logic and clock drivers, as seen in Fig. 1. Chip-to-chip clock tolerance is defined as the difference between worst-case delay and best-case delay of the clock tree measured from point A to point B. This tolerance is due to process variation, temperature difference, and supply voltage variation. Because of the clock tolerance, longer machine cycle is incurred which reduces machine performance. If the delay differences between worst-case delay and best-case delay of each logic stage used in the clock distribution tree are reduced, the tolerance of the whole tree can therefore be reduced. The tolerance of each stage can be reduced by using PMOS pull-up loads which are biased with a special tolerance detector circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Tolerance-Compensated Circuit for Cmos Vlsi Clock Distribution

In a conventional computer system, clock distribution on chip clocks is distributed through a tree of AND-OR logic and clock drivers, as seen in Fig. 1. Chip-to-chip clock tolerance is defined as the difference between worst-case delay and best-case delay of the clock tree measured from point A to point B. This tolerance is due to process variation, temperature difference, and supply voltage variation. Because of the clock tolerance, longer machine cycle is incurred which reduces machine performance. If the delay differences between worst-case delay and best-case delay of each logic stage used in the clock distribution tree are reduced, the tolerance of the whole tree can therefore be reduced. The tolerance of each stage can be reduced by using PMOS pull-up loads which are biased with a special tolerance detector circuit. This tolerance detector circuit controls the charging current of the pull-up load in such a way that the best-case delay is brought closer to the worst-case delay, thereby reducing tolerance. A 3x3 AND-OR-INVERT (AOI) circuit (Fig. 2) is designed with two PMOS pull-up load devices (Q1 and Q2). The gates of the two pull-up devices are controlled by a tolerance detection circuit which contains three stages (T1- R1, T2-R2, T3-R3). The resistors can be implemented with polysilicon or diffused resistors without additional process steps. The circuit operates in the following manner. If the...