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Non-Maskable Interrupt Arbitration

IP.com Disclosure Number: IPCOM000039978D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Hausman, KA: AUTHOR [+3]

Abstract

A technique is described whereby a non-maskable interrupt (NMI) arbitration is implemented so as to allow for the processing of catastrophic errors in computers using multi-master system operation. The concept enables the CPU to gain and maintain control of the system bus until error processing is complete. It is assumed that the Central Arbitration Unit has access to the NMI signal at the CPU. When an NMI is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system. The Central Arbitration Unit will preempt for the bus on behalf of the CPU. When the active master releases the bus, the Central Arbitration Unit generates an ARB State (+ARB/-GRANT=1) to keep all external masters off the bus.

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Non-Maskable Interrupt Arbitration

A technique is described whereby a non-maskable interrupt (NMI) arbitration is implemented so as to allow for the processing of catastrophic errors in computers using multi-master system operation.

The concept enables the CPU to gain and maintain control of the system bus until error processing is complete. It is assumed that the Central Arbitration Unit has access to the NMI signal at the CPU.

When an NMI is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system. The Central Arbitration Unit will preempt for the bus on behalf of the CPU. When the active master releases the bus, the Central Arbitration Unit generates an ARB State (+ARB/-GRANT=1) to keep all external masters off the bus. As the CPU gains control of the bus, the "+ARB/-GRANT" signal will remain high. The last part of the NMI service routine should contain a write to the Central Arbitration Unit's diagnostic port to reset the priority mode.

(Image Omitted)

NOTE:

No Preempt is needed - CPU has control of the bus,

but NMI will force an Arbitration state so as to

keep the masters off the bus during the NMI

routine.

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