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TECHNIQUES for PARASITIC CAPACITANCE MINIMIZATION

IP.com Disclosure Number: IPCOM000039979D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 37K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR

Abstract

In the design of integrated circuits, ideal circuit elements (i.e., transistors, resistors and capacitors) cannot be obtained because of the unavoidable presence of parasitic elements. These parasitic elements, which are a function of the physical dimensions and layout of the devices, as well as the doping profile, result in a deterioration of performance. In MOSFET circuits where nodal impedance is inherently (Image Omitted) high, even small amounts of parasitic capacitance can affect the high frequency response of amplifying circuits. The following discussion provides techniques for minimizing the parasitic capacitance associated with resistor and transistor elements in a MOSFET process. When P-N junction isolation is used as seen in Fig.

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TECHNIQUES for PARASITIC CAPACITANCE MINIMIZATION

In the design of integrated circuits, ideal circuit elements
(i.e., transistors, resistors and capacitors) cannot be obtained because of the unavoidable presence of parasitic elements. These parasitic elements, which are a function of the physical dimensions and layout of the devices, as well as the doping profile, result in a deterioration of performance. In MOSFET circuits where nodal impedance is inherently

(Image Omitted)

high, even small amounts of parasitic capacitance can affect the high frequency response of amplifying circuits. The following discussion provides techniques for minimizing the parasitic capacitance associated with resistor and transistor elements in a MOSFET process. When P-N junction isolation is used as seen in Fig. 1, the depletion region 1 formed by the reverse biased junction between opposite conductivity types (P and N) forms a parasitic capacitor which becomes significant at high frequencies. The depletion region width is a function of the applied bias and the doping levels of the P and N materials. Since the doping levels of the sidewall differs from the floor doping, the capacitance is divided into two components, the area component Ca and the perimeter component Cp. The capacitance is related to the depletion width and, therefore, is a function of the doping levels and the reverse voltage. The form of the capacitance expression is: TECHNIQUES FOR PARASITIC CAPACITANCE MINIMIZATION - Continued where
Cja is the capacitance per unit area of the floor component Cjp is the capacitance per unit area of the perimeter component

d = 0.31

b = 0.50

Vr = reverse voltage applied to the P-N junction

Wc = the contact potential The area and perimeter coefficients, Cja and Cjp, as well as the exponential terms, d and b, are very process dependent and usually are experimentally determined. TECHNIQUES FOR PARASITIC CAPACITANCE MINIMIZATION - Continued The usual way of making a diffusion resistor 2 (Fig. 1) is to open a window in the thick oxide insulation above the silicon surface and implant the open region to form the resistor. Contacts 3 and 4 are placed at the ends of the diffusion and the value of the resistor is determined by the product of the sheet resistivity rho and the length between contacts Lr divided by the resistor width W: R = (rho Lr)/W The resulting structure is a resistor with a distributed capacitance to the P substrate. This capacitance represents a shunt path to the substrate, and at high frequencies can be a limiting factor in circuit performance. A way of minimizing this capacitance will now be described. Cross-sectional profiles for very large-scale integration (VLSI) processes are very complex, often

1

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involving different doping concentrations on each side of a diffusion, e.g., Fig. 2. Consider the N+ diffusion for the enhancement mode device. One side borders on ROX (recessed oxide) and another side borders on polysilicon (the gat...