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Multiple-Input Composite XOR Circuit Implementation

IP.com Disclosure Number: IPCOM000039981D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Smith, GE: AUTHOR

Abstract

Implementation of XOR (Exclusive-OR) circuits from standard logic gates requires a large number of stages for applications, such as a parity tree. The disclosed multiple-input XOR circuit imnplementation significantly reduces the chip area required for such applications with savings in power and speed of operation. Two cases of the disclosed implementation of multiple-input XOR circuits are shown in Fig. 1, a 4-way configuration [A] and an 8-way [B]. In each case, XOR blocks 1 are connected in a cascode-like manner to perform the logic function. As each level of the parity tree adds about 0.2 volt to the logic down level, a level shifter 2 is needed to return the logic level to that required for modified DTL circuits. (Image Omitted) Fig. 2 shows a basic two-input XOR circuit (1 in the Fig. 1 configurations).

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Multiple-Input Composite XOR Circuit Implementation

Implementation of XOR (Exclusive-OR) circuits from standard logic gates requires a large number of stages for applications, such as a parity tree. The disclosed multiple-input XOR circuit imnplementation significantly reduces the chip area required for such applications with savings in power and speed of operation. Two cases of the disclosed implementation of multiple-input XOR circuits are shown in Fig. 1, a 4-way configuration [A] and an 8-way [B]. In each case, XOR blocks 1 are connected in a cascode-like manner to perform the logic function. As each level of the parity tree adds about 0.2 volt to the logic down level, a level shifter 2 is needed to return the logic level to that required for modified DTL circuits.

(Image Omitted)

Fig. 2 shows a basic two-input XOR circuit (1 in the Fig. 1 configurations). Transistors T1 and T2 employ integrated high barrier Schottky diodes (not shown) as antisaturation diodes, and D1 and D2 are low barrier Schottky diodes. Fig. 3 shows the level shifter circuit (2 in the Fig. 1 configurations). Two cases, a 4-way [A] and an 8-way [B] are illustrated. The transistors T3 in each version employ the high barrier Schottky diode 5 as an antisaturation clamp. In addition, a low barrier Schottky 6 is used in the 8-way level shifter circuit. The level shifter circuits are simply modified DTL stages with offset input thresholds. As the height of the tree determines the required thresh...