Browse Prior Art Database

Preferred Load Circuit for a Differential Cascode Voltage Switch Logic Tree

IP.com Disclosure Number: IPCOM000039984D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Thoma, NG: AUTHOR

Abstract

This article describes a load circuit for a differential cascode voltage switch logic tree utilizing precharge devices. In conventional differential cascode voltage switch logic trees are clocked to form a precharge-discharge logic. An inherent part of the circuit is a ground return interrupt device that is shut off to prevent DC current flow during the precharge conditioning portion of (Image Omitted) the operating cycle. This is a non-logic performing device which takes both layout room on the chip, and power to drive the gates. The circuit arrangement disclosed herein eliminates this ground interrupt device to regain the layout room. Also, electrical inadequacies of the conventional circuit are addressed, and it is shown how the modification that eliminates the ground interrupt device also solves the electrical inadequacy.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Preferred Load Circuit for a Differential Cascode Voltage Switch Logic Tree

This article describes a load circuit for a differential cascode voltage switch logic tree utilizing precharge devices. In conventional differential cascode voltage switch logic trees are clocked to form a precharge-discharge logic. An inherent part of the circuit is a ground return interrupt device that is shut off to prevent DC current flow during the precharge conditioning portion of

(Image Omitted)

the operating cycle. This is a non-logic performing device which takes both layout room on the chip, and power to drive the gates. The circuit arrangement disclosed herein eliminates this ground interrupt device to regain the layout room. Also, electrical inadequacies of the conventional circuit are addressed, and it is shown how the modification that eliminates the ground interrupt device also solves the electrical inadequacy. The original circuit is shown in Fig. 1. T1 and T2 are the precharge devices, with T2 being the ground interrupt device. The precharge pulse goes from its normally positive level to a ground level, turning on P channel device T1 and shutting off the ground interrupt device T2. Ct represents the internal differential logic network distributed capacitance. As T1 turns on, the gates of T3 and T4 go positive. Since these two devices form an inverter, the QNOT output goes negative in turn, turning on device T5, which is used to keep the same two gates from forming a floating node once the precharge signal goes positive again. With the inclusion of T5 the circuit forms a stable latch. The difficulty with the circuit is that the distributed capacitance that is shown as Ct is in fact a highly variable quantity which varies with the combinatorial function performed by the cascode logic tree. Since the charging time of Ct varies with the exact value of this internal capacitance, the negative- going edge of the QNOT output varies in time giving a scatter to the negative- going edge. If this cascode logic tree is used to generate a clock or other gating signal, then this skew could cause unreliable gating of the clocked load. Also, since the rise time across Ct varies, the output transition speed can also vary, and the over...