Browse Prior Art Database

High Speed Message Buffers for Input/Output Processors to Minimize Buffer Not-Available Messages

IP.com Disclosure Number: IPCOM000039995D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Chisholm, DR: AUTHOR

Abstract

A technique is described whereby high speed data buffers, and associated logic circuitry, enable various input/output computer processors to maximize the utilization of a single shared input/output (I/O) bus. So as to maximize the utilization of the I/O bus, data is buffered into three slave message buffers so as to minimize the number of buffer not-available (BNA) occurrences. Typically, an I/O bus is an asynchronous bus which supports a multiple number of I/O bus units (IOBU) and is a term for any bus unit which is addressable on the I/O bus, which may be input/output processors (IOPs), the central processing unit (CPU) or a processor sharing IOPs. IOP 11, as shown in Fig. 1, is typical of an input/output processor, utilizing Base-Z 10 to control the transfer of data between host processor 12 and I/O devices 21, 22 and 23.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 27% of the total text.

Page 1 of 4

High Speed Message Buffers for Input/Output Processors to Minimize Buffer Not-Available Messages

A technique is described whereby high speed data buffers, and associated logic circuitry, enable various input/output computer processors to maximize the utilization of a single shared input/output (I/O) bus. So as to maximize the utilization of the I/O bus, data is buffered into three slave message buffers so as to minimize the number of buffer not-available (BNA) occurrences. Typically, an I/O bus is an asynchronous bus which supports a multiple number of I/O bus units (IOBU) and is a term for any bus unit which is addressable on the I/O bus, which may be input/output processors (IOPs), the central processing unit (CPU) or a processor sharing IOPs. IOP 11, as shown in Fig. 1, is typical of an input/output processor, utilizing Base-Z 10 to control the transfer of data between host processor 12 and I/O devices 21, 22 and 23. Device control hardware 20 may be completely integrated within IOP 11 or distributed in the I/O attachments, depending upon the I/O subsystem requirements. The concept provides for additional IOPs 28 and 29 which may be added, each coupled to I/O devices 30 and 31, and may include a co-host processor 27, all interconnected by I/O bus
32.

(Image Omitted)

Host processor 12 includes processor unit 24, main storage 25 and bus control unit (BCU) 26 that provides for the attachment to I/O bus 32. IOP 11 includes internal microprocessor (MP) bus 41 for interconnecting Base-Z 10, direct memory access controller (DMAC) 17, microprocessor (MP) 19, storage unit 18 and device control hardware 20. Device control hardware 20 allows communication between IOP 11 and various I/O devices 21, 22 and 23, via interface bus 42. Base-Z 10 provides attachment of IOP 11 to I/O bus 32 for communication with host processors 12 and 27. Base-Z 10 includes control hardware 14 to control the flow of information from address/data bus 34 through address/data register 13 into or out of high speed memory array buffer 16 by means of internal data path 36, controlled by internal control signals 35. Response is achieved by means of proper handshaking sequences on control bus 33 during various I/O bus sequences. Control hardware 14 also controls the flow of information from microprocessor data bus 40 through microprocessor data register 15 into or out of high speed memory array buffer 16, responding with the proper handshaking sequences required on microprocessor control bus 39 during various microprocessor bus sequences. The two basic sequences for the transfer of information on the I/O bus are the message and storage sequences. Write message-N is the primary means of conveying control information for the transfer of data between IOBUs on the I/O bus. There are other types of messages defined by the I/O bus architecture that are used for initialization and do not require IOP code interpretation of the message data content. These messages are not buffer...