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IBM System/370 Emulator Micro-Instruction Portion Implemented in Master-Slice (Gate Array) Logic

IP.com Disclosure Number: IPCOM000040026D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Hannon, ES: AUTHOR [+2]

Abstract

A described concept simplifies the design and enhances the performance of the IBM System/370 Emulator Assist Processor (EAP) attached to a Reduced Instruction Set Computer (RISC). The EAP micro-instruction consists of a 32-bit control instruction and a 32-bit "skeleton" instruction. The skeleton instruction is a partially complete RISC instruction with a format defined by the RISC Architecture. The skeleton instruction may have only the opcode field with all other fields zero, or have the opcode and some register or displacement fields initialized. The definition of the skeleton instruction is controlled by the micro-programmer, and assembled and linked as part of the microcode load module. The micro-programmer codes a control instruction and skeleton instruction for each required step in emulating a S/370 instruction.

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IBM System/370 Emulator Micro-Instruction Portion Implemented in Master- Slice (Gate Array) Logic

A described concept simplifies the design and enhances the performance of the IBM System/370 Emulator Assist Processor (EAP) attached to a Reduced Instruction Set Computer (RISC). The EAP micro-instruction consists of a 32-bit control instruction and a 32-bit "skeleton" instruction. The skeleton instruction is a partially complete RISC instruction with a format defined by the RISC Architecture. The skeleton instruction may have only the opcode field with all other fields zero, or have the opcode and some register or displacement fields initialized. The definition of the skeleton instruction is controlled by the micro- programmer, and assembled and linked as part of the microcode load module. The micro-programmer codes a control instruction and skeleton instruction for each required step in emulating a S/370 instruction. The control portion of the EAP micro-instruction is executed by the EAP hardware, and specifies how register or displacement fields from the S/370 instruction are mapped into the skeleton instruction fields (Fig. 1). It also selects the skeleton instruction to be used. The set of control instructions is loaded into (static) random- access memory (RAM) during system start-up (initial microcode load).

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The skeleton instruction set is implemented as follows: 1) Microcode (control and skeleton instructions) is assembled and linked, 2) Post processor run to generate an EAP microcode file, 3) APL program run to separate skeleton instructions and perform logic reduction, and 4) Logic reduction output incorporated into chip design as the skeleton instruction table. The skeleton instruction set is implemented in a chip as a logic table with the 8-bit address field as inputs and the 32 instruction bits as outputs (Fig. 2). To minimize logic circuits, the table can be reduced manually by looking for common terms during the design process or by using the output of the APL log...