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V-Groove Gallium Arsenide Junction FET

IP.com Disclosure Number: IPCOM000040030D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Broom, RF: AUTHOR

Abstract

A junction FET is proposed that is built on a GaAs substrate having a V-shaped groove. Formed on top of an n-channel which extends over the planar and the grooved surface is a molecular beam epitaxy (MBE) deposited amphoterically doped GaAs layer. Because of the crystal orientation dependence, the conductivity of this layer is n+ in the planar regions and p+ on the walls of the groove. The p+ section and the underlaying n-channel provide the desired junction. Use is made of the phenomenon that the conductivity type obtained with Si doping during the growth of GaAs by molecular beam epitaxy (MBE) is dependent on the crystal orientation of the substrate. For example, on a (100) surface the Si occupies Ga sites, resulting in n-type material, while on (111) planes the Si substitutes for As, thereby making the GaAs p-type.

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V-Groove Gallium Arsenide Junction FET

A junction FET is proposed that is built on a GaAs substrate having a V-shaped groove. Formed on top of an n-channel which extends over the planar and the grooved surface is a molecular beam epitaxy (MBE) deposited amphoterically doped GaAs layer. Because of the crystal orientation dependence, the conductivity of this layer is n+ in the planar regions and p+ on the walls of the groove. The p+ section and the underlaying n-channel provide the desired junction. Use is made of the phenomenon that the conductivity type obtained with Si doping during the growth of GaAs by molecular beam epitaxy (MBE) is dependent on the crystal orientation of the substrate. For example, on a (100) surface the Si occupies Ga sites, resulting in n-type material, while on (111) planes the Si substitutes for As, thereby making the GaAs p-type. The basic steps of the process used to fabricate the FET are illustrated in the drawings. First, V-shaped grooves are etched in the (100) surface of a semi-insulating GaAs substrate 1, using a plane- selective etchant so that the walls of the groove lie on (111) planes. The channel 2 is then grown by MBE, using a group VI dopant impurity (e.g., S or Se) to ensure that the channel is n-type, regardless of crystal orientation (Fig. A). On completion of the channel, the dopant element is changed to Si and growth continued for a further 100-200 nm to form a layer 3, comprising p+ and n+ regions, as shown in Fig. B. At this...