Browse Prior Art Database

Synch Lock for Vertical Deflection IC

IP.com Disclosure Number: IPCOM000040033D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Ainscow, F: AUTHOR [+2]

Abstract

A circuit is disclosed for use in association with a fixed frequency commercial TV vertical deflection integrated circuit (IC) which enables the IC to be synchronized to a wide range of frequency about the fixed frequency. The IC is set to run freely, then the circuit applies synch pulses to stop the IC oscillator, and, lastly, applies modified synch pulses to reset the IC ramp generator directly. In CRT display design the most cost-effective vertical deflection is achieved with the aid of a commercial consumer TV IC. However, these devices are intended for use at fixed frame rates (UK 50 Hz, USA 60 Hz) and, as such, have a limited capture range of a few hertz about the free run frequency. The circuit to be described is a specific implementation for use with the Philips TDA1670A.

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Synch Lock for Vertical Deflection IC

A circuit is disclosed for use in association with a fixed frequency commercial TV vertical deflection integrated circuit (IC) which enables the IC to be synchronized to a wide range of frequency about the fixed frequency. The IC is set to run freely, then the circuit applies synch pulses to stop the IC oscillator, and, lastly, applies modified synch pulses to reset the IC ramp generator directly. In CRT display design the most cost-effective vertical deflection is achieved with the aid of a commercial consumer TV IC. However, these devices are intended for use at fixed frame rates (UK 50 Hz, USA 60 Hz) and, as such, have a limited capture range of a few hertz about the free run frequency. The circuit to be described is a specific implementation for use with the Philips TDA1670A. Principle of Operation Positive-going synch pulses are fed to point A. Clamping by Q1 base charges C1 so that Q1 is cut off between pulses. AC coupled synch pulses from point A are fed to the base of Q1 via C1, causing Q1 to conduct for the duration of the pulse. Hence, Q1 collector falls to near 0 volts during the synch pulse. During the low level time of the input synch pulse a potential divider is formed by R6 D2 and Ro. The value of R6 being chosen such that the base of the internal transistor on pin 4 of the TDA1670A is a volt or so reverse biased, disabling the internal oscillator and preventing the ramp generator from resetting. As soon as the...