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Improving the Correction of Soft Errors in Presence of Hard Ones

IP.com Disclosure Number: IPCOM000040034D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Glaise, R: AUTHOR

Abstract

This article describes a method for correcting most cases of one soft error in the presence of hard errors in the data stored in a memory, based upon the invert/non-invert concept. The inability to correct all cases of soft errors in the presence of two hard ones comes from the fact that inverting, before storing back the word, does not help if only one hard error is masked. For a given pattern the following may occur: Memory bits "stuck at" . . . . 0 . . 0 . . . . .

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Improving the Correction of Soft Errors in Presence of Hard Ones

This article describes a method for correcting most cases of one soft error in the presence of hard errors in the data stored in a memory, based upon the invert/non-invert concept. The inability to correct all cases of soft errors in the presence of two hard ones comes from the fact that inverting, before storing back the word, does not help if only one hard error is masked. For a given pattern the following may occur: Memory bits "stuck at" . . . . 0 . . 0 . . . . .2 bits stuck at 0 Pattern to store x x
x x 0 x x 1 x x x x x Pattern has 1 bit different of the

"stuck at" Inverted

Pattern x x x x 1 x x 0 x x x x x Pattern has 1 bit different of the "stuck at" Clearly, when a soft error disturbs one bit at a memory address where 2 hard errors are already present, there is a 50% chance that the pattern stored at this location will allow the correction (the 2 bits are both equal to or different from the clamps) and a 50% chance that inversion does not change the situation (1 bit is masked while the 2nd is unmasked). Before and after inversion a 2-bit error is detected. When the above occurs, there is still, however, a possibility to correct the pattern. The method which is described hereafter is based on the remark that the position of the hard errors is known after inversion and given by a comparator, part of the error correcting code (ECC) hardware, used by the refresh routine to find the memory locations having more than 2 hard clamps. Let us look at an example using the H matrix shown on the top of the next page.

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Now assume that there is 1 soft error (S) at bit 3 in byte 0, 1 hard error masked (M) at bit 2 in byte 1 and 1 hard error unmasked (H) at bit 5 in byte
X. The syndrome is then 00100010 (Soft error + Left Hard error (not masked)). After the inversion error at bit 6 in byte X is masked, the soft error remains and there is one hard error unmasked at bit 2 in byte 1. The syndrome is then 10100011 (Soft error + Right Hard error + Inversion). Because one knows the position of the 2 hard errors (result of the comparator after i...