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Precision Phase and Frequency Discriminator

IP.com Disclosure Number: IPCOM000040035D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Lee, ACF: AUTHOR

Abstract

A phase, frequency discriminator is disclosed for controlling an oscillator with minimum phase jitter, high speed locking to a reference signal and locking from any initial frequency. Two falling edge detectors are used, the output of each inhibiting the output of the other, thereby improving phase and frequency control by removing delays in reset circuitry from the control path, and preventing glitches in the output when a reset is occurring. The logic for the phase/frequency discriminator is shown in Fig. 1. The circuit consists of two falling edge detectors, reset logic, and switching logic to prevent glitches on reset and inhibit the outputs.

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Precision Phase and Frequency Discriminator

A phase, frequency discriminator is disclosed for controlling an oscillator with minimum phase jitter, high speed locking to a reference signal and locking from any initial frequency. Two falling edge detectors are used, the output of each inhibiting the output of the other, thereby improving phase and frequency control by removing delays in reset circuitry from the control path, and preventing glitches in the output when a reset is occurring. The logic for the phase/frequency discriminator is shown in Fig. 1. The circuit consists of two falling edge detectors, reset logic, and switching logic to prevent glitches on reset and inhibit the outputs. Because the logic is sequential, the states of all the SR latches are undefined on start-up, and hence there is a period of settling before the operation of the circuit is entirely predictable. This settling period has a well-defined end, the definition of which depends on whether the loop is trying to do phase or frequency corrections. For frequency correction the settling period is over when a reset occurs on the trailing edge of the lower frequency input signal. For phase correction the settling period is over when a reset occurs on a trailing edge of the lagging input waveform. After the settling period, the operation again depends on whether the discriminator is performing phase or frequency correction.

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As an example of frequency correction, consider the case where the reference frequency, on XTAL, is greater than the variable frequency, on RET. RET is the return signal from the VCO controlled by the discriminator. The waveforms for this case are shown in Fig. 2. When frequency correction is being performed, all the reset pulses occur on the trailing edges of the lower frequency input waveform, RET. After a reset, the first edge detector to find a trailing edge will always be on the higher frequency input, i.e., XTAL in this case, and edge detector 1. The edge detector output is latched and holds the UP output active through the output switching. Thus the charge pump is told to increase the VCO control voltage and hence t...