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Peripheral Logic for Writable Control Stores

IP.com Disclosure Number: IPCOM000040042D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Mori, F: AUTHOR

Abstract

This article describes peripheral logic for writable control stores (WCSs) associated with a bit slice sequencer. The logic has a configuration employing universal shift registers (USRs) for transfer of data to and from the WCSs. This configuration enables the reduction of necessary parts, substrate space and cost in contrast to conventional arrangements using transceivers and pipeline registers. The figure shows an embodiment including plural WCSs, i.e., WCS1 plural USRs, i.e., USR1 ... USRn+2, and a bit slice sequencer. Each USR has both serial and parallel data transfer functions. The USR2 - USRn+2 are connected in series to shift data bits serially through them. In initial loading or diagnosing, the data (i.e.

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Peripheral Logic for Writable Control Stores

This article describes peripheral logic for writable control stores (WCSs) associated with a bit slice sequencer. The logic has a configuration employing universal shift registers (USRs) for transfer of data to and from the WCSs. This configuration enables the reduction of necessary parts, substrate space and cost in contrast to conventional arrangements using transceivers and pipeline registers. The figure shows an embodiment including plural WCSs, i.e., WCS1 plural USRs, i.e., USR1 ... USRn+2, and a bit slice sequencer. Each USR has both serial and parallel data transfer functions. The USR2 - USRn+2 are connected in series to shift data bits serially through them. In initial loading or diagnosing, the data (i.e., microcode) to be written into the WCS1 - WCSn is loaded eight bits by eight bits, for example, into the USR2 by a host processor (not shown) through an external bus. The eight bits in the USR2 are shifted to the USR3, while contents in the latter are shifted to the next USR. In this shift operation, the USR1 is used as a shift counter. To this end, the USR1 has its shift-in terminal tied up to a potential Vcc, and it is reset to all zeros each time the USR2 is loaded with the eight bits. Then the USR1 performs the shift of the shifted-in "1" bit in synchronism with the shift operation of the USR2 and produces a flag signal on its shift-out terminal when the eight-bit pattern has been shifted out. Thus, in re...