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Support Circuitry for Local Bus Integrity Checking in Robotics Applications

IP.com Disclosure Number: IPCOM000040070D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Alewine, NJ: AUTHOR [+5]

Abstract

This article describes a circuit arrangement which enhances the safe operation of a robot manipulator by insuring the integrity of a local bus used by robot controllers. The circuit arrangement, disclosed herein, is being applied to a robot which utilizes a processor card in conjunction with an interface card to provide control to a single motor. The processor provides desired positions as well as the control algorithm. The interface card, which is connected to the processor card through a local bus, provides the interface to the motor amplifier and position feedback circuitry. Fig. 1 is a block diagram which represents the relationship of the local bus with the other elements of the motor control system. Fig.

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Support Circuitry for Local Bus Integrity Checking in Robotics Applications

This article describes a circuit arrangement which enhances the safe operation of a robot manipulator by insuring the integrity of a local bus used by robot controllers. The circuit arrangement, disclosed herein, is being applied to a robot which utilizes a processor card in conjunction with an interface card to provide control to a single motor. The processor provides desired positions as well as the control algorithm. The interface card, which is connected to the processor card through a local bus, provides the interface to the motor amplifier and position feedback circuitry. Fig. 1 is a block diagram which represents the relationship of the local bus with the other elements of the motor control system. Fig. 2 is a block diagram of the elements required in the circuit arrangement of this disclosure for the bus integrity check. It allows a comprehensive check of all signal lines through the bus by holding the last address accessed in a latch. Every time an eight-bit I/O read or write is executed, the status of the address lines is loaded into

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the latch. The latch can then be read to obtain the previous address after a read or write. Since the read, write, data, and address lines must all be functioning normally to wrap the address lines back through the data lines, bus integrity can be insured.

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