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Branchable INSTRUCTION BUFFER for Cacheless Machines

IP.com Disclosure Number: IPCOM000040071D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Curley, LD: AUTHOR [+2]

Abstract

The purpose of a cache is to allow the fast accessing of instructions and to free main storage from re-accessing instructions each time they are repeated. In a system without a cache a means of preventing the instruction fetch process from tying up the main storage interface with repeated instruction fetches is needed. One method of accomplishing this is to implement a fully accessible dual-port instruction buffer with such features as immediate access to any loaded instruction, parallel read and write capability, partial buffer load capability with a marking system to keep track of valid entries, and wait capability for a branch ahead in the buffer to entries not yet loaded from memory. There are a few natural additions to this buffer which make it more flexible for non-sequential execution. 1.

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Branchable INSTRUCTION BUFFER for Cacheless Machines

The purpose of a cache is to allow the fast accessing of instructions and to free main storage from re-accessing instructions each time they are repeated. In a system without a cache a means of preventing the instruction fetch process from tying up the main storage interface with repeated instruction fetches is needed. One method of accomplishing this is to implement a fully accessible dual-port instruction buffer with such features as immediate access to any loaded instruction, parallel read and write capability, partial buffer load capability with a marking system to keep track of valid entries, and wait capability for a branch ahead in the buffer to entries not yet loaded from memory. There are a few natural additions to this buffer which make it more flexible for non-sequential execution. 1. Filling the portion of the Instruction Buffer from

the point the processor is requesting to the end

of the page. Assume that one memory fetch may not

cross a "Page Boundary", i.e., 16 bytes, 32 bytes,

64 bytes, etc., depending on machine size and

configuration), and the Instruction streams which

begin in the middle or end of some "page" force a

fetch from the entry point in the page to the end

of the page only. Chances of branching back to

the beginning of the page are small.

2. Being able to reissue an instruction already sent,

if the processor requests it (assuming it is in

the buffer) without re-accessing main storage.

This is good for Instruction loops which are less

than one page.

3. Branching ahead in the buffer to an instruction

not yet received from memory and holding until it

is loaded and sent to the processor. The following abstract is one implementation of a branchable buffer: A limitation of the memory requires that all memory fetches be on 8-byte boundaries,
i.e., 8, 16, 24, or 32 bytes in length. The largest memory fetch that can be made is 32 bytes. Shown in the top of the drawing is a 32-byte instruction buffer arranged in a 4-byte-wide by 8-li...