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Watchdog Timer and One-Shot to Insure Safe Operation of a Robotic Manipulator

IP.com Disclosure Number: IPCOM000040072D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Alewine, NJ: AUTHOR [+4]

Abstract

This article describes an integrity check circuit arrangement utilizing a watchdog timer and one-shot for use by a robotic system which enhances the safe operation of a robot manipulator by causing motor power to be disabled in the event of processor failures. Robot motors are dependent on the integrity of slave processors for their controlled operation. Accordingly, a means of checking the processors in realtime is required. The circuit arrangement, disclosed herein, provides this integrity check. It can be applied to a robot which utilizes an STD bus with a single master and multiple slave processor cards. Each slave processor controls a single motor of a tool or manipulator joint. The master processor provides the interface between the controller and the user. Both cards are based on the Intel 8088 microprocessor.

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Watchdog Timer and One-Shot to Insure Safe Operation of a Robotic Manipulator

This article describes an integrity check circuit arrangement utilizing a watchdog timer and one-shot for use by a robotic system which enhances the safe operation of a robot manipulator by causing motor power to be disabled in the event of processor failures. Robot motors are dependent on the integrity of slave processors for their controlled operation. Accordingly, a means of checking the processors in realtime is required. The circuit arrangement, disclosed herein, provides this integrity check. It can be applied to a robot which utilizes an STD bus with a single master and multiple slave processor cards. Each slave processor controls a single motor of a tool or manipulator joint. The master processor provides the interface between the controller and the user. Both cards are based on the Intel 8088 microprocessor. On the master card, an interrupt is generated every ten milliseconds and the code and stack segment registers are checked. If the registers are found to be within valid memory, a poll of all slave cards is made to insure that each card is in control. Since each card resets an integrity bit every one millisecond, the master card need only test and set the integrity bit to check slave card integrity. On each slave card, an interrupt is generated every one millisecond in order to check the processor and to signal the master card that the slave card is functioning normally. This is accomplished by...