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Horizontal Synchronizing Signal Generator

IP.com Disclosure Number: IPCOM000040088D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Aoki, T: AUTHOR [+3]

Abstract

A horizontal synchronizing (H-SYNC) signal generator comprises means for maintaining stability of the H-SYNC signal when a number of columns to be displayed is changed. As shown in Fig. 1, a display station includes a flip-flop 7 for producing a H-SYNC signal. The flip-fop 7 is adapted to be set by an output of a comparator 5 and reset by an output of an another comparator 6. Each comparator receives an output of a column counter 8 on one of its two input terminals. Assuming that the display is operable in either 80- or 132-column mode, the column counter 8 is caused to count from "0" to "99" repeatedly in response to a clock signal of first frequency in the 80-column mode. In the 132-column mode, the column counter 8 is caused to count from "0" to "164" repeatedly in response to a clock signal of second frequency.

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Horizontal Synchronizing Signal Generator

A horizontal synchronizing (H-SYNC) signal generator comprises means for maintaining stability of the H-SYNC signal when a number of columns to be displayed is changed. As shown in Fig. 1, a display station includes a flip-flop 7 for producing a H-SYNC signal. The flip-fop 7 is adapted to be set by an output of a comparator 5 and reset by an output of an another comparator 6. Each comparator receives an output of a column counter 8 on one of its two input terminals. Assuming that the display is operable in either 80- or 132-column mode, the column counter 8 is caused to count from "0" to "99" repeatedly in response to a clock signal of first frequency in the 80-column mode. In the 132-column mode, the column counter 8 is caused to count from "0" to "164" repeatedly in response to a clock signal of second frequency. A microprocessor (not shown) operates to load predetermined data into a first start register 1 and a first end register 2. The data in the register 1 indicates a column at which the H-SYNC signal should start, while the data in the register 2 indicates a column at which the H-SYNC signal should end. These data are transferred to a second start register 3 and a second end register 4 in response to a "LATCH CLOCK" signal which is generated at a suitable instant. The comparator 5 produces the output to set the flip-flop 7 when the column count of the counter 8 gets equal to the data in the register 3, while the co...