Browse Prior Art Database

Divider Line for Display

IP.com Disclosure Number: IPCOM000040091D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Nojima, K: AUTHOR [+3]

Abstract

This article describes a circuit for displaying one or more horizontal divider lines to divide a display screen into multiple areas. The circuitry shown in Fig. 1 is operable to define a special row consisting of three scan lines, wherein the middle scan line is brightened as the divider line. For example, row N is defined as the special row, while rows N-1 and N+1 are normal lines, as shown in Fig. 2. In Fig. 1, a line attribute register is loadable with a line attribute for each row. The line attribute for the row to show the divider line includes a particular bit to enable a line decoder. The enabled line decoder operates to decode a line count output form a line counter which is incremented in synchronism with the scan lines.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Divider Line for Display

This article describes a circuit for displaying one or more horizontal divider lines to divide a display screen into multiple areas. The circuitry shown in Fig. 1 is operable to define a special row consisting of three scan lines, wherein the middle scan line is brightened as the divider line. For example, row N is defined as the special row, while rows N-1 and N+1 are normal lines, as shown in Fig. 2. In Fig. 1, a line attribute register is loadable with a line attribute for each row. The line attribute for the row to show the divider line includes a particular bit to enable a line decoder. The enabled line decoder operates to decode a line count output form a line counter which is incremented in synchronism with the scan lines. When the line count is 0 or 2, the line decoder generates Force-0 signal to

(Image Omitted)

cause the scan line 0 or 2 to remain dark. On the other hand, when the line count is 1, the decoder generates Force-1 signal to cause the scan line 1 to brighten. When the line count gets to 3, the decoder issues a reset signal to reset the line counter via an OR gate.

1

Page 2 of 2

2

[This page contains 5 pictures or other non-text objects]