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Interrupt Arbitration in Personal Computer Systems

IP.com Disclosure Number: IPCOM000040102D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+4]

Abstract

A technique is described whereby an interrupt arbitration is implemented so as to prevent an overrun condition on unbuffered interrupt devices in computers using multi-master system operation. The concept enables the CPU to gain and maintain control of the system bus until a programmable time is reached. The timing involved is dependent on the speed of the interrupt processing and must be optimized for each application. It is assumed that the Central Arbitration Unit has access to the INTR signal at the CPU. When an INTR is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system. The Central Arbitration Unit will preempt for the bus on behalf of the CPU.

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Interrupt Arbitration in Personal Computer Systems

A technique is described whereby an interrupt arbitration is implemented so as to prevent an overrun condition on unbuffered interrupt devices in computers using multi-master system operation. The concept enables the CPU to gain and maintain control of the system bus until a programmable time is reached. The timing involved is dependent on the speed of the interrupt processing and must be optimized for each application. It is assumed that the Central Arbitration Unit has access to the INTR signal at the CPU. When an INTR is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system. The Central Arbitration Unit will preempt for the bus on behalf of the CPU. When the active master releases the bus, the Central Arbitration Unit generates an ARB State (+ARB/-GRANT=1) to keep all external masters off the bus. As the CPU gains control of the bus, the "+ARB/-GRANT" signal will remain high. The time allotted to the processor for the interrupt is programmable and must be optimized for each application. A timer starts when the processor receives the bus, in the ARB State, and stops when the programmed time is reached. At that time, the bit in the diagnostic port is reset, and the special priority mode is reset, also. The value the timer is programmed for must represent a period of time that exceeds the execution time for the interrupt service...