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Simplified Cascode Reference Generation

IP.com Disclosure Number: IPCOM000040113D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Carter, EL: AUTHOR [+2]

Abstract

A typical cascode current switch circuit (Fig. 1), which can be used in very large-scale integration logic chips, has a 3.4v power supply to define two cascode signal levels. (A two-way XOR function is depicted.) One level is centered around Vref-1, and the other is centered around Vref-2. These two voltage references are distributed throughout the chip, and they are generated by on-chip reference circuits. For a good output drive capability, the outputs are generated (Image Omitted) by emitter follower stages. Both the current switch and the emitter followers are biased with constant current sources, which are driven by another distributed reference voltage (Iref).

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Simplified Cascode Reference Generation

A typical cascode current switch circuit (Fig. 1), which can be used in very large-scale integration logic chips, has a 3.4v power supply to define two cascode signal levels. (A two-way XOR function is depicted.) One level is centered around Vref-1, and the other is centered around Vref-2. These two voltage references are distributed throughout the chip, and they are generated by on-chip reference circuits. For a good output drive capability, the outputs are generated

(Image Omitted)

by emitter follower stages. Both the current switch and the emitter followers are biased with constant current sources, which are driven by another distributed reference voltage (Iref). The functionality of this type of circuit can be enhanced by defining additional cascode levels, without the penalties normally associated with an additional complex reference distribution. A three-way XOR circuit (Fig.
2) is designed with three cascode levels. As shown, the additional cascode level requires another reference distribution. This additional reference is undesirable, however, because the usage of three-level cascode circuits is typically low. (The more frequently used two-level cascode circuits would be penalized

(Image Omitted)

by the loss of a wiring channel used to distribute the additional reference.) Also, this reference voltage is relatively difficult to distribute because it is only approximately 300 mv below the 3.4v power supply. To allow...