Browse Prior Art Database

Memory Bus Switch Logic Unit

IP.com Disclosure Number: IPCOM000040135D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Moriguchi, S: AUTHOR [+2]

Abstract

In a terminal controller comprising multiple control units and memory banks in which one of the control units is for controlling the communication with a main controller or host processor connected thereto and for receiving instructions and data for the other control units from the main controller and selectively storing them in the memory banks and the other control units are for controlling the associated I/O devices connected thereto using the instructions and data stored in the memory banks, the terminal controller is provided with a memory bus switch logic unit for controlling the selective connection of one of the control units to one of the memory bands so that each of the control units is connected to access the desired one of the memory banks independently of the other control units.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

Memory Bus Switch Logic Unit

In a terminal controller comprising multiple control units and memory banks in which one of the control units is for controlling the communication with a main controller or host processor connected thereto and for receiving instructions and data for the other control units from the main controller and selectively storing them in the memory banks and the other control units are for controlling the associated I/O devices connected thereto using the instructions and data stored in the memory banks, the terminal controller is provided with a memory bus switch logic unit for controlling the selective connection of one of the control units to one of the memory bands so that each of the control units is connected to access the desired one of the memory banks independently of the other control units. As shown in the drawing, each of the control units and memory banks has a dedicated data-address bus and memory bank control information bus. The memory bank control information on the bus includes an identification of the control unit involved, an identification of the memory bank to be connected thereto, and operational signals for the decode circuit. In response to the information, the decode circuit provides a control signal to the bus selector circuit for controlling the connection of the control unit to the memory bank, as identified by the memory bank control information. In the same manner as above, any of the control units can be connect...