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Residue Checking and Signal Processors

IP.com Disclosure Number: IPCOM000040142D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Jones, GD: AUTHOR

Abstract

The residue checking technique is utilized for concurrent error detection in a signal processor, as disclosed herein. The arithmetic section of the signal processor consists of a group of registers organized in a stack 1, an arithmetic logic unit (ALU) 2, and a parallel multiplier 3. Operands enter and exit the arithmetic section of the processor via a common data bus (CDB) 7. A 16-bit-wide data flow is assumed, although the checking technique is applicable to other data flow widths as well. The residue checking approach disclosed appends to all operands a predicted residue (PR). All operations on each operand will update the PR. The operand can be validated by computing the actual residue (R) and comparing it to the predicted PR.

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Residue Checking and Signal Processors

The residue checking technique is utilized for concurrent error detection in a signal processor, as disclosed herein. The arithmetic section of the signal processor consists of a group of registers organized in a stack 1, an arithmetic logic unit (ALU) 2, and a parallel multiplier 3. Operands enter and exit the arithmetic section of the processor via a common data bus (CDB) 7. A 16-bit- wide data flow is assumed, although the checking technique is applicable to other data flow widths as well. The residue checking approach disclosed appends to all operands a predicted residue (PR). All operations on each operand will update the PR. The operand can be validated by computing the actual residue (R) and comparing it to the predicted PR. The approach utilized performs validation at the interfaces between the arithmetic section and the common data bus 7. The validation occurs when operands are transferred to and from the data memory or to I/O. Checking at this point in the flow path monitors the effects of transmission through any of the flow paths, multiplexers and arithmetic functions that are included in the circuitry. The residue check effectively "sees" the majority of the operations, and if any error has occurred in any of the various elements, it should be uncovered at this point. Residues based on modulo 15 are used within the flow of the arithmetic unit itself. Modulo 15 insures an average checking accuracy of 93%, which is a level suitable for high reliability applications. Four checking bits are appended to each operand to encode the PR. Modulo 3 residues are used with operands on the common data bus 7 to transfer data between the arithmetic unit 2 and the data memory or I/O (not shown). The modulo 3 check is used because the required two check bits for modulo 3 residues can replace the two parity bits that are commonly used with halfword data stores in processors. This yields approximately the same level of checking performance for this portion of the interface. As shown in the figure, the checking function consists of three major elements. The residue prediction circuit 4 for the ALU 2 is the first element, the residue prediction circuit 5 for the multiplier 3 is the second, and the validation and conversion circuit 6 between arithmetic unit 2 and the data bus 7 is the third element. The ALU residue prediction circuit 4 derives it inputs from the input selection circuit 8, which consists of the A multiplexer 8A and the B multiplexer 8B. These inputs consist of the A and B operands and their predicted residues from register stack 1 and the output selection circuit 9 connected thereto. The function of this ALU prediction circuit 4 is to compute the predicted residue, PR (0) of an outcome 0, from residue prediction equations for arithmetic, logical and shift rotate operations. Modulo 15 prediction equations are employed and these equations are known from general literature in the field and...