Browse Prior Art Database

Pc-Based Driver Card for Stress Testing of Components Such As Integrated Circuit Chips

IP.com Disclosure Number: IPCOM000040157D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 110K

Publishing Venue

IBM

Related People

Ford, JV: AUTHOR [+2]

Abstract

During sample stress test of components such as integrated circuit chips, for example, within an oven, each of the components is exercised and monitored under both high temperature stress and temperature cycling stress. The failure detection capabilities are limited to detecting functional failures. Parametric failures such as an output current being outside of the specification, for example, do not cause a functional failure that can be detected. An IBM prototype card 1 (Fig. 1A), which is employed with an IBM PC (personal computer), utilizes the output of a 74154 four-to-sixteen decoder 2 to selectively address one of twelve 74374 latch arrays 3-14 (Fig. 1B). The latch arrays 3-8 are used to write data from the PC to one of 48 chips to be exercised.

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Pc-Based Driver Card for Stress Testing of Components Such As Integrated Circuit Chips

During sample stress test of components such as integrated circuit chips, for example, within an oven, each of the components is exercised and monitored under both high temperature stress and temperature cycling stress. The failure detection capabilities are limited to detecting functional failures. Parametric failures such as an output current being outside of the specification, for example, do not cause a functional failure that can be detected. An IBM prototype card 1 (Fig. 1A), which is employed with an IBM PC (personal computer), utilizes the output of a 74154 four-to-sixteen decoder 2 to selectively address one of twelve 74374 latch arrays 3-14 (Fig. 1B). The latch arrays 3-8 are used to write data from the PC to one of 48 chips to be exercised. Each of the chips has six gates serially connected to each other with a first gate of the chip having the data written therein and the last gate of the six serially connected gates having the data read therefrom when the corresponding latch array of the latch arrays 9-14 is addressed from the IBM PC.

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The writing and reading does not necessarily occur in sequence for the same chip. That is, several of the chips could be written in one sequence and reading could be in another sequence. The latch arrays 3-8 are connected through outputs 001-048 of connectors T01 to a ribbon cable that leads to the components within th...