Browse Prior Art Database

Interrupt Arbitration to Prevent Data Overrun

IP.com Disclosure Number: IPCOM000040167D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+3]

Abstract

A technique is described whereby an interrupt arbitration is implemented so as to prevent an overrun condition on unbuffered interrupt devices in computers using multi-master system operation. The concept enables the CPU to maintain a higher percent of system processing time during the servicing of interrupts. Interrupt performance is improved by allowing the CPU to execute bus cycles during the time that masters are competing for the bus, when "+ARB/-GRANT" is high. The number of CPU bus cycles may be programmable. It is assumed that the Central Arbitration Unit has access to the INTR signal at the CPU. When an INTR is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system.

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Interrupt Arbitration to Prevent Data Overrun

A technique is described whereby an interrupt arbitration is implemented so as to prevent an overrun condition on unbuffered interrupt devices in computers using multi-master system operation. The concept enables the CPU to maintain a higher percent of system processing time during the servicing of interrupts. Interrupt performance is improved by allowing the CPU to execute bus cycles during the time that masters are competing for the bus, when "+ARB/-GRANT" is high. The number of CPU bus cycles may be programmable. It is assumed that the Central Arbitration Unit has access to the INTR signal at the CPU. When an INTR is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system. During normal operation, the CPU is the lowest priority device on the system and may only own the bus for one cycle during an ARB State if masters are constantly competing for the bus. The special priority allows the CPU multiple cycles during the ARB State. The number of bus cycles allotted to the processor during each ARB State is programmable and must be optimized for each application. This technique allows the interrupt processing to be faster than normal. Although hardware enables the priority feature, software must disable it. The necessary code should be located at the end of the highest priority interrupt, "IRQO". The purpose of the code is to reset the pr...