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Self-Aligned Technique Employing Planarized Resist for Reducing Poly-Silicon Sheet Resistance by Formation of a Metal Silicide

IP.com Disclosure Number: IPCOM000040169D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Bausmith, RC: AUTHOR [+3]

Abstract

Utilizing existing CMOS (complementary metal-oxide-semiconductor technologies, a process that includes a combination of self-planarizing materials with separate self-aligned silicide (salicide) formations on gates and diffusions that allows for independent sheet resistance (Rs) optimization without an additional mask level is described. Currently, polysilicon resistance is reduced by the use of silicides. It is difficult to optimize shallow junction contact resistance without some degree of compromise. Circuit performance improvements can be realized by utilizing a novel approach allowing flexibility in the choice of metals for silicide formation on polysilicon gates and shallow junctions of a field-effect transistor. Fig. 1 shows a standard CMOS device structure before metal silicide is used to reduce the sheet resistance.

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Self-Aligned Technique Employing Planarized Resist for Reducing Poly- Silicon Sheet Resistance by Formation of a Metal Silicide

Utilizing existing CMOS (complementary metal-oxide-semiconductor technologies, a process that includes a combination of self-planarizing materials with separate self-aligned silicide (salicide) formations on gates and diffusions that allows for independent sheet resistance (Rs) optimization without an additional mask level is described. Currently, polysilicon resistance is reduced by the use of silicides. It is difficult to optimize shallow junction contact resistance without some degree of compromise. Circuit performance improvements can be realized by utilizing a novel approach allowing flexibility in the choice of metals for silicide formation on polysilicon gates and shallow junctions of a field-effect transistor. Fig. 1 shows a standard CMOS device structure before metal silicide is used to reduce the sheet resistance. Fig. 2 shows a layer of low-pressure chemical-vapor deposition (LPCVD) Si3N4 covering the base structure followed by a thick layer of a planarizing resist which is etched back below the top of the gate polysilicon. Fig. 3 shows the structure before sinter and after a selective reactive ion etch (RIE) step used to remove the nitride layer where it is exposed above the resist. Note that the junction regions are still covered by nitride. The resist is then removed, and a refractory metal is evaporated or deposited, follo...