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High Performance Floating Point Execution

IP.com Disclosure Number: IPCOM000040177D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Rodriguez, JR: AUTHOR

Abstract

A technique is described whereby a common design approach is used for a series of floating-point (FP) processors where the goal of maximum cost/performance is preserved in each case. The common design approach is made possible by the definition of a model that implements high performance features of the floating-point processor under the floating- point architecture. The model, therefore, is a representation of the preferred high performance implementation for a series of processors. Floating-point code is optimized in accordance with the model. Compilers which follow the model will generate code capable of capitalizing on the particular design features of a complete series of machines.

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High Performance Floating Point Execution

A technique is described whereby a common design approach is used for a series of floating-point (FP) processors where the goal of maximum cost/performance is preserved in each case. The common design approach is made possible by the definition of a model that implements high performance features of the floating-point processor under the floating- point architecture. The model, therefore, is a representation of the preferred high performance implementation for a series of processors. Floating-point code is optimized in accordance with the model. Compilers which follow the model will generate code capable of capitalizing on the particular design features of a complete series of machines. With the advent of Reduced Instruction Set Complexity (RISC) type of architecture as used in processing units (PUs), the use of organizational techniques, such as instruction overlap and pipelining, permit execution rates of a single cycle per instruction. FP instructions, however, cannot typically be executed in a single cycle. For this reason, the FP processor has been defined as a separate unit attached to the PU through a central bus called the Processor Bus (PBUS). The

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goal of the floating-point architecture is to provide high performance of FP intensive code by means of organizational techniques complementary to those used in the PU to obtain single-cycle execution of non-FP code. The overlap in the execution of PU instructions, with the execution of FP instructions in the FPU and the overlap of several instructions in the FPU through the use of pipelining and multiple execution units, provides the means of high performance execution of intensive code. This creates a dependency on the code sequence to be optimized to take advantage of these features. The underlying framework for the use of the model is illustrated in the block diagram of Fig. 1. FP architecture definition 10 permits implementations which vary over a wide range including low performance implementations where code execution is serialized at the PBUS at one end to high performance implementations, taking maximum advantage of instruction overlap. Processor implementations, such as hardware models 11 and 12 and compiler implementation 13, would have a great deal of alternatives for the implementation of the architecture. Given that the FP architecture has been optimized for high performance FP execution, still preserving the inherent flexibility, and given the importance of high performance execution of FP intensive code, it is assumed that only implementations of th...