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Browse Prior Art Database

Fullword Even Branch

IP.com Disclosure Number: IPCOM000040195D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Frye, HE: AUTHOR [+4]

Abstract

Described is a Fullword Even branch in a processor wherein microcode can determine which half of a doubleword storage data register contains the first byte of data. Normally, when HMC (Horizontal Microcode) fetches from memory, an "aligned doubleword fetch" is performed. The low 3 bits of the address provided by HMC (which specify a particular byte within the doubleword) are not sent to the memory. Thus the first byte of arbitrarily aligned data may be in either the left or the right fullword of the storage data register. In order to assist in fetching objects which may cross a double- word boundary, the processor has an "unaligned doubleword fetch" capability. If the address of the data to be fetched is in the left fullword of a doubleword (an "Even fullword"), then the hardware performs a double word fetch from memory.

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Fullword Even Branch

Described is a Fullword Even branch in a processor wherein microcode can determine which half of a doubleword storage data register contains the first byte of data. Normally, when HMC (Horizontal Microcode) fetches from memory, an "aligned doubleword fetch" is performed. The low 3 bits of the address provided by HMC (which specify a particular byte within the doubleword) are not sent to the memory. Thus the first byte of arbitrarily aligned data may be in either the left or the right fullword of the storage data register. In order to assist in fetching objects which may cross a double- word boundary, the processor has an "unaligned doubleword fetch" capability. If the address of the data to be fetched is in the left fullword of a doubleword (an "Even fullword"), then the hardware performs a double word fetch from memory. If the address of the data to be fetched is in the right half of a doubleword (an "Odd fullword"), then the hardware performs a doubleword fetch which includes that address, discards the Even fullword (i.e., the first four bytes), and puts the Odd fullword in the right half of the storage data register specified by the HMC. The hardware then performs another doubleword fetch of the next doubleword, discards the Odd fullword, and puts the Even fullword into the left half of the storage data register. Note that this results in the desired data appearing to be "backward" in the storage data register, i.e., the first byte is some...