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Continuous Variable Slope Delta Modulation Timing and Control for Audio Circuitry

IP.com Disclosure Number: IPCOM000040199D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Kuo, J: AUTHOR [+2]

Abstract

A technique is described whereby continuous variable slope delta (CVSD) modulation circuitry is improved through the addition of data buffering and control circuitry, so as to extend record and playback timing windows, as used in audio recording and playback sections of personal computers (PCs). The addition of data buffering and control circuitry enables the PC processor to execute a variety of tasks without encountering contention problems. As a result, additional software applications enable voice data to be used interactively with the keyboard for messaging or voice annotation programming.

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Continuous Variable Slope Delta Modulation Timing and Control for Audio Circuitry

A technique is described whereby continuous variable slope delta (CVSD) modulation circuitry is improved through the addition of data buffering and control circuitry, so as to extend record and playback timing windows, as used in audio recording and playback sections of personal computers (PCs). The addition of data buffering and control circuitry enables the PC processor to execute a variety of tasks without encountering contention problems. As a result, additional software applications enable voice data to be used interactively with the keyboard for messaging or voice annotation programming. In the prior art, upon the execution of an interrupt in the CVSD, as it is recording at set baud rates, the PC processor must perform an input/output (I/O) read operation of the voice data within a set period of time, after the shift register is full. By incorporating data buffer unit 10, as shown in the figure, along with control circuitry supplied by CVSD unit 11, for record and playback modes, the processor will have an extended period of time to perform other activities, such as random-access memory refresh, time-of-day clock, keyboard interrupt and other interrupt functions. Data buffer unit 10 is able to be read while data is shifted into shift register
12. The time window between I/O read requests and the first bit shift-in is thereby extended. A similar data flow is applied for voice p...