Browse Prior Art Database

Method of Obtaining Diagnostic Data With Limited RAM

IP.com Disclosure Number: IPCOM000040200D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Westcott, GR: AUTHOR

Abstract

Diagnostic information about a complete mechanism cycle can be obtained with limited controller storage by recording data during different portions of successive cycles. Referring to the figures, serial controller 1 is in a distributed processor architecture and interfaces with main processor 2 along parallel bus 3 and with several local controllers 4 along serial interface, two-wire bus 5. Controllers 1 and 4 each have limited random- access memory (RAM), most of which is required for operation of the attached mechanism. In this illustration, controller 4 operates a printer carriage while others (not shown) may operate a print band, stacker, ribbon or hammer unit.

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Method of Obtaining Diagnostic Data With Limited RAM

Diagnostic information about a complete mechanism cycle can be obtained with limited controller storage by recording data during different portions of successive cycles. Referring to the figures, serial controller 1 is in a distributed processor architecture and interfaces with main processor 2 along parallel bus 3 and with several local controllers 4 along serial interface, two-wire bus 5. Controllers 1 and 4 each have limited random- access memory (RAM), most of which is required for operation of the attached mechanism. In this illustration, controller 4 operates a printer carriage while others (not shown) may operate a print band, stacker, ribbon or hammer unit. Diagnostic scan data is obtained by adding tri-state AND gates 6-9 to input/output ports 10 that are either spare or not continuously used and gating, in multiplex fashion, the data signals required for measurement or adjustment. For example, a diagnostic controller scan (DCS) signal gates the ANDs for driver 11 input signals and its output signals to motor 12. The gated outputs from ANDs 6-9 are transmitted via bus 13 to the input ports at controller
4. In operation, main processor 2 calculates End of Frame (EOF) count for the operation to be scanned and a timer count, and issues a start operation command, such as Carriage Go, to serial controller 1, which activates carriage controller 4. Controller 4 provides two initial functions: it decrements th...