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State Space Structure of Digital Filters

IP.com Disclosure Number: IPCOM000040202D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Sinha, B: AUTHOR

Abstract

A technique is described whereby digital filters utilize state space structure implementation, so as to minimize errors due to finite word length limitations. The technique is unique in that throughout the pipelining structure, no new zeros are created which would normally require pole-zero cancellation, thereby reducing hardware circuit requirements and improving overall performance of the filter. Described is the use of digital filter difference equations and pipelining equations in the development and implementation of the state space structure so that no new zeros are created requiring pole-zero cancellation.

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State Space Structure of Digital Filters

A technique is described whereby digital filters utilize state space structure implementation, so as to minimize errors due to finite word length limitations. The technique is unique in that throughout the pipelining structure, no new zeros are created which would normally require pole-zero cancellation, thereby reducing hardware circuit requirements and improving overall performance of the filter. Described is the use of digital filter difference equations and pipelining equations in the development and implementation of the state space structure so that no new zeros are created requiring pole-zero cancellation. A digital filter of order N can be represented in the following difference equation: The corresponding transfer function is: which, in terms of a delay operator D, is By applying the technique for pipelining, for p stage pipelining, equation (3) becomes: Putting equation (4) in transfer function format, it becomes: which, in the Z domain, is Note that the presence of Z-(p+1), delay operator of the order of (p+1) in the feedback loop, provides the pipelining of the filter with (p+1) stages. Since pole-zero cancellation is required, this leads to expensive hardware implementation. Alternatively, the stable digital filter of equations (1) and (2) can be put into state space structures as follows: where one of the possible set of state matrices is: From equation (7) Substituting into equation (7a) we get Continuing for p steps, we have In equation (9), the state space recursive equation, to compute Xk+1 state, we need only Xk-p+1, not Xk, which is the _ _ immediate past state.

This provides for the implementation shown in Fig. 1. The double lines indicate vector data flow. It should be noted that the feedback path has a delay of Z-p. Summing node does not need the immediate past Xk, _ but only

Xk-p+1, thereby allowing the p-stage pipelined _ implementation in the feedback p...