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Self-Timed Performance Test for Stand-Alone Random-Access Memories

IP.com Disclosure Number: IPCOM000040209D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Belansek, GM: AUTHOR [+3]

Abstract

A method for reducing the effective tester timing tolerance of memory access measurements by moving the output comparator from the tester to the chip is reported. Tester pulse timing tolerances and propagation delays are significant undesirable variables when screening high performance random- access memory (RAM) products for a guaranteed access times. To accommodate tester pulse timing tolerances and tester pulse propagation delays, chips are designed to a tighter worst-case performance specification than would otherwise be required to prevent shipment of out of specification product. By negating the tester pulse timing tolerances and timing pulse propagate delays between tester and wafer chips under test, more precise access measurements can be made.

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Self-Timed Performance Test for Stand-Alone Random-Access Memories

A method for reducing the effective tester timing tolerance of memory access measurements by moving the output comparator from the tester to the chip is reported. Tester pulse timing tolerances and propagation delays are significant undesirable variables when screening high performance random- access memory (RAM) products for a guaranteed access times. To accommodate tester pulse timing tolerances and tester pulse propagation delays, chips are designed to a tighter worst-case performance specification than would otherwise be required to prevent shipment of out of specification product. By negating the tester pulse timing tolerances and timing pulse propagate delays between tester and wafer chips under test, more precise access measurements can be made. This allows the removal of excessive guard band margins while meeting the product access specification. By moving the output comparator circuit from the tester to the chip, the tester can be recalibrated for every chip tested. The accuracy of the test pulse (TP) delay relative to the chip select pulse (CS) is guaranteed with the use of the on-chip circuit when used in conjunction with a simple initial tester routine applied to each RAM chip tested. The tester recalibration consists of two parts: 1) A tester pulse calibration to compensate for design

tolerances inherent in the electronics of the tester. 2)

Measure the on-chip propagation delay of the TP to adjust the skew between the CS pulse and TP sample timing. This insures

that the sample time will be within the required chip

access time specification for the product being screened. To compensate for tester design tolerances, a dlatch (L1) circuit with its output driver is physically placed on a chip between input pads CS and TP, as shown in the figure. This circuit is used to compare tester timing pulses TP and CS, and with the aid of a software routine in the tester, inherent tester timing pulse tolerances are "zeroed out". When these tester pulses are emitted, the pulses travel separate paths 1 and 2 and meet at L1. The tester "shmoos" TP with respect to CS and monitors the L1 out pad until the tester finds the relative timing between the TP and CS, where L1 is set for a "1"/"0" within the least signific...