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SYNCHRONIZED DUAL 8051 SHARED RAM SYSTEM

IP.com Disclosure Number: IPCOM000040210D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Marshall, JR: AUTHOR

Abstract

The Intel 8051 family of microprocessors is very popular for control functions. As the required functions increase, many applications find that two processors are required. Although the 8051 has a serial port which permits some degree of intercommunication between two processors, this capability is limited and a shared random-access memory (RAM) is a desirable alternative. This approach is difficult to implement, however, because the 8051 architecture does not include any easy way to stop the processor, or slow down a memory cycle if a resource is not ready when accessed. The present embodiment provides a clock stretching and synchronizing circuit which causes the instruction cycles in two 8051's to be 50% out of phase with each other.

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SYNCHRONIZED DUAL 8051 SHARED RAM SYSTEM

The Intel 8051 family of microprocessors is very popular for control functions. As the required functions increase, many applications find that two processors are required. Although the 8051 has a serial port which permits some degree of intercommunication between two processors, this capability is limited and a shared random-access memory (RAM) is a desirable alternative. This approach is difficult to implement, however, because the 8051 architecture does not include any easy way to stop the processor, or slow down a memory cycle if a resource is not ready when accessed. The present embodiment provides a clock stretching and synchronizing circuit which causes the instruction cycles in two 8051's to be 50% out of phase with each other. This permits each pro

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cessor to access a shared RAM during the time when the other processor cannot make such access. All cycle are interleaved such that no arbitration function is required. Fig. 1 shows a block diagram of the present embodiment. The circled number in each block is that of the figure showing details of that logic. The overall functions are as follows. It is seen that the two processors used are 1, an 8031 Master, and 2, an 8051 Slave. The figure shows that while oscillator 3 inputs directly to Master 1, its input to Slave 2 is controlled by Clock Counter 4 and Clock Stretcher 5. Clock Counter 4 counts the number of cycles that 1 and 2 are out of phase and inputs that number to Master 1, on request. If the count is too low, 1 and 2 are less than 50% out of phase. Master 1 then enables Clock Stretcher 5 to delay Slave 2 one more cycle. This continues until the correct count is achieved. When this occurs, Bus Switch 6 is en SYNCHRONIZED DUAL 8051 SHARED RAM SYSTEM - Continued abled by Master 1 and its output line proceeds to toggle in synch with out-of-phase processors. This toggling output determines which processor the shared RAM 10 is assigned to at any given time. Input to Address Control MUX 8 enables addressing assignment. Input to Shared RAM Strobes 7 controls Data MUX Latches 9 and enables data bus assignment. Refer to Fig. 2, Clock Counter. (In all of the Figs. 2 - 8, circled numbers show which figure the logic lines run to or from.) Flip-flop 21 is normally held low by Enable line 22 connected to its Clear input. After Enable 22 is turned on (23) by the Master Processor (Fig. 8), flip-flop 21 is set by the next negative transition 25 of 8031 RD line 24, thus producing positive transition 27 at output A, line 26. Flip- flop 28 is normally held high by Enable line 22 connected to its Clear input, and therefore its output B, line 29, is high. With lines 26 and 29 both high, together with the input from 8031 (12 MHZ), AND block 31 generates output C, line 32, as a gated oscillator input

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to 6-Stage Ring Counter 33. Counter 33 proceeds to count incoming pulses on line 32, with outputs Q0-5, line 34, inputting...