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ADDRESSING HARDWARE for MERGING/SEPARATING DATA SEGMENTS

IP.com Disclosure Number: IPCOM000040214D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Sibbers, DE: AUTHOR

Abstract

Simplified addressing hardware is used to merge or separate groups of contiguous data segments when the lengths of such segments are binary powers. Addressing to combine segments of data (Fig. 1) from Data Segment Area 11 in RAM (random-access memory) 10 with segments of data from Data Segment Area 12 in RAM 10 takes advantage of properties of binary powers, allowing addressing to be implemented with a single incrementing address register. (Image Omitted) Three requirements are: 1. The length of the data segments must be a binary power. 2. The starting location of the Data Segment Areas must be divisible without remainder by the length of the smaller segment. 3.

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ADDRESSING HARDWARE for MERGING/SEPARATING DATA SEGMENTS

Simplified addressing hardware is used to merge or separate groups of contiguous data segments when the lengths of such segments are binary powers. Addressing to combine segments of data (Fig. 1) from Data Segment Area 11 in RAM (random-access memory) 10 with segments of data from Data Segment Area 12 in RAM 10 takes advantage of properties of binary powers, allowing addressing to be implemented with a single incrementing address register.

(Image Omitted)

Three requirements are:

1. The length of the data segments must be a binary

power.

2. The starting location of the Data Segment Areas

must be divisible without remainder by the length

of the smaller segment.

3. The starting location of the Data Segment Area

having the smaller length has a portion of its

address which is derived from the starting

location of the Data Segment Area having the

larger length and thus cannot be arbitrarily

assigned. Fig. 2 shows the hardware required for addressing. It consists of a split Address Register 30, a two-legged Address Selector 40, and Control Logic 50. The following symbols are used to explain the implementation: A = binary power of the length of the smaller data

segment.

B = binary power of the length of the larger data

segment less the binary power of the length of the

smaller segment.

C = remaining address bits needed to address the full

range of RAM 10. ADDRESSING HARDWARE FOR

MERGING/SEPARATING
DATA SEGMENTS - Continued D = fixed address bits to be used as high-order bits

when addressing the smaller data segments. These

may, if desired, be furnished by a

non-incrementing register. For purposes of explanation, consider that the smaller data segment will precede the larger data segment. The sequence of operations is as follows: 1. Control Logic 50 logically isolates the two

portions of Address Register 30 and selects le...