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Browse Prior Art Database

Dynamic Relocation of Memory (For Error Recovery)

IP.com Disclosure Number: IPCOM000040220D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 58K

Publishing Venue

IBM

Related People

Coffman, RL: AUTHOR [+4]

Abstract

A technique is described whereby a computer memory is analyzed for errors, through the use of a diagnostic program, so that the errors may be isolated to enable the affected error segment (memory banks) to be electrically replaced by a segment of error-free memory. The diagnostic program reorganizes all of the error-free memory segments into a contiguous usable memory array. Two methods of implementation are discussed. In prior art, errors occurring during the diagnostic testing of computer memory at start-up time required replacement of a defective memory segment before useful computer operation could proceed. The two concepts, discussed herein, provide for the remapping of memory errors during diagnostic testing by relocating the memory so that the computer will be usable.

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Dynamic Relocation of Memory (For Error Recovery)

A technique is described whereby a computer memory is analyzed for errors, through the use of a diagnostic program, so that the errors may be isolated to enable the affected error segment (memory banks) to be electrically replaced by a segment of error-free memory.

The diagnostic program reorganizes all of the error-free memory segments into a contiguous usable memory array. Two methods of implementation are discussed. In prior art, errors occurring during the diagnostic testing of computer memory at start-up time required replacement of a defective memory segment before useful computer operation could proceed. The two concepts, discussed herein, provide for the remapping of memory errors during diagnostic testing by relocating the memory so that the computer will be usable. The first method discussed allows a defective segment of memory to be disabled and the low-order segment of memory to be located at the lower boundary of the disabled segment. The second

(Image Omitted)

method allows the memory banks to be reorganized such that the defect is placed in the high-order bank. The error segment is relocated into the high end of the memory space. Memory in the defective segment, below the defective byte, is made contiguous with the known good memory, so that all good memory is made available to the user. A memory expansion circuit card, as shown in Fig. 1, is used to implement either method. The card can contain up to two megabytes of memory in increments of 512 Kbyte banks and is designed so as to be utilized in an IBM AT Personal Computer (PC). The card is designed so as to be overlaid in place of a detected defective memory bank of memory located anywhere in the address space of the PC. This overlay process is accomplished by means of the programmable option select (POS) bits produced by POS circuit 10 and is accomplished without user interaction. Twelve POS bits are used.

Bit 0 controls the gating of the memory card output. When bit 0 is low, all memory card outputs are de-gated. This effectively removes the card from the input/output (I/O) channel. Bits 1 to 3 enable and disable memory banks 1, 2, and 3, and can enable and disable in any order, combination or at any time. Bits 4 to 10 select the starting address for the memory card.

(Image Omitted)

To illustrate the operation of the first method, assume a total system configuration, as shown in Fig. 2. During power-up, the diagnostics detect a hard error in bank 2 of memory card 1. The dynamic memory relocation concept utilizes the POS bits to disable bank 2. Also, bank 3 would also be disabled since all banks above the bad bank of the memory card must be disabled for the purpose of overlaying the bad memory. Memory card 2, banks 0 and 1 are overlaid into address

1

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space ordinarily occupied by memory card 1, banks 2 and 3, as shown in Fig. 3. The user is notified of the failure and is allowed to continue to operate i...