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Serial Test Clock Circuit Interface for Gate Arrays

IP.com Disclosure Number: IPCOM000040253D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Lee, WR: AUTHOR [+2]

Abstract

A technique is described whereby a circuit interface allows the use of any number of test clocks for gate array testing, while requiring only three input/output (I/O) pins. It is an improvement over prior designs which were limited to only 16 internal test clocks. The circuit is so designed that serial test clock interfaces use three signal I/O signal pins on gate array circuitry of shift registers and demultiplexers, as shown in the figure. The three signal I/O pins are address input 10, address strobe 11 and test clock 12. Address input 10 signal and address strobe 11 signal control shift register 13 inside a gate array. Address strobe 11 is used as a clock to strobe the address input data into shift register 13.

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Serial Test Clock Circuit Interface for Gate Arrays

A technique is described whereby a circuit interface allows the use of any number of test clocks for gate array testing, while requiring only three input/output (I/O) pins. It is an improvement over prior designs which were limited to only 16 internal test clocks. The circuit is so designed that serial test clock interfaces use three signal I/O signal pins on gate array circuitry of shift registers and demultiplexers, as shown in the figure. The three signal I/O pins are address input 10, address strobe 11 and test clock 12. Address input 10 signal and address strobe 11 signal control shift register 13 inside a gate array. Address strobe 11 is used as a clock to strobe the address input data into shift register
13. The parallel outputs of shift register 13 are presented as a binary address to a standard demultiplexer (DMX) circuit 14, where its enable signal is controlled by test clock 12. When test clock 12 signal is driven active, the test clock signal, addressed by the shift register outputs will also be driven active. This configuration allows any one of the demultiplexer 14 outputs to be controlled by the test clock input and to be used as a clock for testing sections of logic within the gate array. For example, to use the serial test clock interface to select test clock X in the case where N internal test clocks are used, such that two raised to the Mth power is greater than or equal to N, the following pr...