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Non-Volatile Memory Page

IP.com Disclosure Number: IPCOM000040256D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Taber, AH: AUTHOR

Abstract

Most strategies for replacing magnetic core memory with semiconductor memory have experienced drawbacks. For example, a battery-backed complementary metal-oxide semiconductor (CMOS) static random-access memory (SRAM) approach has a limited temperature range, limited shelf life, and can present a potential chemical hazard depending on battery technology utilized. Correspondingly, the use of electrically erasable programmable read only memories (EEPROMs) alone imposes an unrealistic limitation on the number of write cycles. A strategy which has none of the above limitations and is simple and inexpensive to implement is described in the following.

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Non-Volatile Memory Page

Most strategies for replacing magnetic core memory with semiconductor memory have experienced drawbacks. For example, a battery-backed complementary metal-oxide semiconductor (CMOS) static random-access memory (SRAM) approach has a limited temperature range, limited shelf life, and can present a potential chemical hazard depending on battery technology utilized. Correspondingly, the use of electrically erasable programmable read only memories (EEPROMs) alone imposes an unrealistic limitation on the number of write cycles. A strategy which has none of the above limitations and is simple and inexpensive to implement is described in the following. As shown in the diagram, the strategy involves the use of both a SRAM array for unlimited high speed read/write, and an EEPROM array for non-volatile storage/recall upon power-down/power-up. An energy- storage capacitor provides the power needed to transfer the contents of SRAM to EEPROM during the one to five seconds needed to do so upon detection of an impending power-down condition. On power-up, the contents of EEPROM can be transferred back to SRAM in less than 60 milliseconds. The 10,000 write/erase cycle limit of the EEPROMs allows an average of about three power-up/power-down cycles per day for ten years, which is sufficient for a typical application. The key challenge to this design is in making the EEPROM write operation short enough and the on-board power capacity high enough to enable the store operation to complete on its own after a power interruption. The design thus involves separate power supplies for the memory and support logic. During normal operation, a 12V supply keeps a large capacitor charged, which provides current through a DC/DC converter to power the 5V memory array and RETRIEVE/STORE logic. The remaining logic, whic...