Browse Prior Art Database

Digital Sub-Nanosecond Timing Generator

IP.com Disclosure Number: IPCOM000040257D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Millham, EH: AUTHOR

Abstract

Disclosed is a method for generating timing pulses with sub-nanosecond accuracy using digital techniques. As shown in the figure, an oscillator 10 drives a coarse digital timing circuit 12 which includes a series of counters wherein a "divide by" function occurs resulting in a pulse every Nth oscillator cycle. The generated pulse is delayed by a fine digital timing circuit 14 using a plurality of tapped delay lines or logic block delays and is typically limited to increments of no less than 500 picoseconds. In order to provide delays in increments of less than 500 picoseconds, an output of oscillator 10 is delayed M increments by an oscillator delay circuit 16.

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Digital Sub-Nanosecond Timing Generator

Disclosed is a method for generating timing pulses with sub-nanosecond accuracy using digital techniques. As shown in the figure, an oscillator 10 drives a coarse digital timing circuit 12 which includes a series of counters wherein a "divide by" function occurs resulting in a pulse every Nth oscillator cycle. The generated pulse is delayed by a fine digital timing circuit 14 using a plurality of tapped delay lines or logic block delays and is typically limited to increments of no less than 500 picoseconds. In order to provide delays in increments of less than 500 picoseconds, an output of oscillator 10 is delayed M increments by an oscillator delay circuit 16. Moreover, an output of the oscillator delay circuit 16 and an output of the course digital timing circuit 12 are fed to inputs of an AND gate 18 which facilitates the enabling of the fine digital timing circuit 14. The oscillator 10 has a range which is sufficient to encompass the minimum increment of the fine digital timing circuit 14. Additionally, the fine digital timing circuit 14 has a range which is sufficient to encompass the minimum increment of the course digital timing circuit 12. Multiple timing generators are sourced from a single oscillator and a single oscillator delay circuit.

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